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| ASAHI KASEI AKM CONFIDENTIAL [AK4650] = Preliminary = AK4650 16Bit CODEC with MIC/HP/SPK-AMP & TSC GENERAL DESCRIPTION The AK4650 targeted at PDA and other low-power, small size applications. It features a 16-bit stereo CODEC with a built-in Microphone-Amplifier, Headphone-Amplifier, Speaker-Amplifier and Touch Screen Controller. Input circuits include a Microphone-Amplifier and an ALC (Auto Level Control) circuit. The AK4650 is connected with AC'97 controller (CPU) via AC-Link. The AK4650 is available in a very small 57-BGA, utilizing less board space than competitive offerings. FEATURES 1. Resolution: 16bits 2. Recording Function * Mono Input (Single-ended or Differential Input) * 2 to 1 Selector (Internal and External MIC) * MIC Power: 2 outputs (Internal and External MIC) * 1st MIC Amplifier: +20dB or 0dB * 2nd Amplifier with ALC: +27.5dB -8dB, 0.5dB Step * ADC Performance (@MIC-Amp=+20dB): S/(N+D): 75dB, DR, S/N: 83dB * MIC Detection 3. Playback Function * Digital De-emphasis Filter (tc=50/15s, fs=32kHz, 44.1kHz, 48kHz) * Digital Volume (0dB -63dB, 0.5dB Step, Mute) * Bass Boost * Mono Output - Full-differential Output - S/(N+D): 85dB, S/N: 95dB - Analog Volume: +6dB -15dB, 3dB Step * Headphone-Amp - Output Power: 40mW@16 (HVDD=3.3V) - S/(N+D): 60dB@10mW, S/N: 90dB * Headphone Jack Detection * Mono Speaker-Amp - Output Power: 300mW@8 (HVDD=3.3V, ALC2=OFF) - S/(N+D): 55dB@110mW, S/N: 90dB - BTL Output - ALC (Auto Level Control) circuit * Mono Beep Input * AUX Input - Full-differential Input - Analog Volume: +12dB -34.5dB, 1.5dB Step, Mute * Stereo Line Input - Single-ended Input - Analog Volume: +12dB -34.5dB, 1.5dB Step, Mute REV 0.6 -1- 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] 4. Touch Screen Controller * Two Auxiliary Analog Inputs * Pen Pressure Measurement * Direct Battery Measurement * On-Chip Voltage Reference (2.5V) * 12 bit SAR type A/D Converter 5. System Clock: 24.576MHz, 12MHz, 3.6864MHz 6. Sampling Rate: 48kHz, 44.1kHz, 32kHz, 24kHz, 22.05kHz, 16kHz, 11.025kHz, 8kHz 7. Power Management 8. Audio, Touch Screen & Control I/F: AC-Link I/F 9. Ta = -30 85C 10. Power Supply: 2.7V 3.6V (typ. 3.3V) 11. Package: 57pin BGA (5mm x 5mm) REV 0.6 -2- 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Block Diagram (Audio Block) MICOUT PMMIC AIN MVREF DVDD1 DVSS1 DVDD2 DVSS2 MPE MPI INT MIC Power Supply PR6-0 ALC1 (IPGA) MIC Power Supply ADC MIC-AMP 0dB or 20dB HPF EXT MDT 0.075 x AVDD PMMO RESETN SYNC BITCLK SDATAIN SDATAOUT Audio Interface ATT CPU MOUT+ ATT MOUTPMHPL or PMHPR or PMSPK ATT PR6-0 Control Register DAC DATT SMUTE PLL1 HVDD HVSS HPL PMHPL VRA PR5 PR5 XTO/PLL0 HP-AMP MIX MIX PLL XTI/MCKI HDT PMHPR HPR MUTET HP-AMP MIX MIX VCOC1 PMLIN PMSPK PMAUX SPP VCOC2 Volume Volume Volume MIX SPKAMP SPN MIX ALC2 PMBP MOUT VCOM BEEP AVSS AVDD MIN RIN/MDT MOUT2 LIN/MPE AUXIN+ AUXIN- Figure 1. Block Diagram (Audio Block) REV 0.6 -3- 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Block Diagram (Touch Screen Controller Block) SYNC XP BITCLK YP SDATAIN XN Control Logic SDATAOUT YN IN1 IN2/BEEP IOUT VBAT AIN+ Internal VREF(2.5V) VREF VREF+ VREF- R1 R2 AIN- 12bit ADC (SAR type) INTN Pen Interrupt ADEXE TSVDD TSVSS Figure 2. Block Diagram (TSC Blcok) REV 0.6 -4- 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Ordering Guide AK4650VG AKD4650 57pin BGA (0.5mm pitch) -30 +85C Evaluation board for AK4650 Pin Layout 9 8 7 6 5 4 3 2 1 AK4650 Top View A B C D E F G H J 9 8 7 6 5 4 3 2 1 NC VCOC1 XP YP YN IN1 VREF ADEXE NC A BEEP/IN2 VCOC2 TSVDD XN TSVSS VBAT IOUT INTN DVDD1 B AVDD AVSS VCOM MVREF AUXIN+ AUXIN- MPI INT/MIC- EXT/MIC+ MDT/RIN MPE/LIN AIN MOUT- HPL NC MICOUT MOUT+ HPR HVDD SPN HDT MIN TEST J Top View HVSS SPP NC XTO/PLL0 XTI/MCKI C SDATA OUT DVSS1 D DVSS2 BITCLK E SDATAIN DVDD2 F SYNC RESETN G MUTET MOUT2 PLL1 H REV 0.6 -5- 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Comparison with AK4640 Item Mic Input Mic Detection Mic Power Bass Boost MID Mono Output Volume HP-Amp Output Power Headphone Jack Detection Stereo Beep Input Stereo Line Input AUXIN Volume Audio I/F PLL Input Clock Control I/F Package AK4640 Single-ended Not Available Vout = 0.75 x AVDD +5.94dB@20Hz, fs=44.1kHz +6/-17dB 15mW Not Available Available Not Available +24 -21dB, 3dB step I2S etc. 12.288MHz, 11.2896MHz, 12MHz 4-wire/I2C 52QFN (7.2mm x 7.2mm) and 57BGA (5mm x 5mm) AK4650 Single-ended / Differential Available Vout = 2.2V +10.78dB@20Hz, fs=44.1kHz +6 -15dB, 3dB step 40mW Available Not Available Availble +12 -34.5dB, 1.5dB step, Mute AC-Link 24.576MHz, 12MHz, 3.6864MHz AC-Link 57BGA (5mm x 5mm) Comparison with AK4181 Item Temperature Measurement SYNC Signal Input for ADC Control I/F AK4181 On-chip Sensor Not Available 4-wire AK4650 Current Output for Off-chip Sensor Available AC-Link REV 0.6 -6- 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] PIN/FUNCTION No. A1 B1 C1 C2 D1 D2 E1 E2 F2 F1 G2 G1 H1 Pin Name NC DVDD1 XTI MCKI XTO PLL0 DVSS1 SDATAOUT BITCLK DVSS2 SDATAIN DVDD2 SYNC RESETN PLL1 I/O I I O I I O O I I I Function No Connect Pin No internal bonding. This pin should be connected to the ground. Digital Power Supply 1 Pin X'tal Input Pin External Master Clock Input Pin X'tal Output Pin (PLL1 pin = "L") PLL Input Master Clock Frequency Select 0 Pin (PLL1 pin = "H") "L": 3.6864MHz, "H": 12MHz Digital Ground 1 Pin Serial 256-bit AC'97 data stream from digital controller 12.288MHz(256fs) serial data clock Digital Ground 2 Pin Serial 256-bit AC'97 data stream to digital controller Digital Power Supply 2 Pin AC'97 Sync Clock, 48kHz(1fs) fixed rate sampling rate AC'97 Master Hardware Reset PLL Input Master Clock Frequency Select 1 Pin "L": 24.576MHz (PLL0 pin = "L") "H": 3.6864MHz (PLL0 pin = "L") or 12MHz (PLL0 pin = "H") When PLL1 pin = "H", X'tal oscillation circuit is not available. Test Pin This pin should be connected to the ground. ALC Input Pin Analog Mixing Output Pin Mute Time Constant Control Pin Connected to HVSS pin with a capacitor for mute time constant. Headphone Detect Pin (Internal pull up by 100k) Speaker Amp Positive Output Pin Speaker Amp Negative Output Pin Headphone & Speaker Amp Ground Pin Headphone & Speaker Amp Power Supply Pin Rch Headphone Amp Output Pin Lch Headphone Amp Output Pin Mono Line Negative Output Pin Mono Line Positive Output Pin Analog Input Pin No Connect Pin No internal bonding. This pin should be connected to the ground. J1 J2 H2 H3 J3 H4 J4 H5 J5 J6 H6 H7 J7 H8 J9 TEST MIN MOUT2 MUTET HDT SPP SPN HVSS HVDD HPR HPL MOUT- MOUT+ AIN NC I O O I O O O O O O I - REV 0.6 -7- 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Function Microphone Analog Output Pin Microphone Detect Pin (Internal pull down by 500k) (RNMD bit = "0") G8 Rch Line Input Pin (RNMD bit = "1") MIC Power Supply Pin for External Microphone (LNMP bit = "0") H9 Lch Line Input Pin (LNMP bit = "1") External Microphone Input Pin (Single-ended Input: MDIF bit = "0") G9 Microphone Positive Input Pin (Differential Input: MDIF bit = "1") Internal Microphone Input Pin (Single-ended Input: MDIF bit = "0") F8 Microphone Negative Input Pin (Differential Input: MDIF bit = "1") F9 MIC Power Supply Pin for Internal Microphone E8 Mono AUX Negative Input Pin E9 Mono AUX Positive Input Pin D8 MIC Power Supply Reference Voltage Output Pin Common Voltage Output Pin D9 VCOM O Bias voltage of ADC inputs and DAC outputs. C8 AVSS Analog Ground Pin C9 AVDD Analog Power Supply Pin BEEP I Mono Beep Signal Input Pin (IN/BP bit = "0") B9 IN2 I Auxiliary 2 Analog Input (IN/BP bit = "1") No Connect Pin A9 NC No internal bonding. This pin should be connected to the ground. Output 1 Pin for Loop Filter of PLL Circuit A8 VCOC1 O This pin should be connected to DVSS with a resistor (10k) and a capacitor (4.7nF) in series. Output 1 Pin for Loop Filter of PLL Circuit B8 VCOC2 O This pin should be connected to DVSS with a resistor (10k) and a capacitor (4.7nF) in series. Note: All input pins except analog input pins. No. J8 Pin Name MICOUT MDT RIN MPE LIN EXT MIC+ INT MIC- MPI AUXIN- AUXIN+ MVREF I/O O I I O I I I I I O I I O REV 0.6 -8- 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] No. B7 Pin Name TSVDD I/O - A7 XP I/O A6 YP I/O B6 XN I/O A5 YN I/O B5 B4 A4 B3 A3 B2 A2 C3 TSVSS VBAT VREF IN1 IOUT INTN ADEXE NC I I/O I I/O O I - Function Touch Screen Controller Power Supply Pin Touch Screen X+ plate Voltage Supply Pin X axis Measurement: Supplies the voltage. Y axis Measurement: This pin is used as the input for the A/D converter. Pen Pressure Measurement: This pin is the input to the A/D converter at Z1 measurement. Temperature/VBAT/IN1/IN2 Measurement: OPEN state. Power-down State: is pulled up by an internal resistor (typ.50k ohm). Touch Screen Y+ plate Voltage Supply Pin Y axis Measurement: Supplies the voltage. X axis Measurement: This pin is used as the input for the A/D converter. Pen Pressure Measurement: Supplies the voltage. Temperature/VBAT/IN1/IN2 Measurement: OPEN state. Power-down State: OPEN state. Touch Screen X- plate Voltage Supply Pin X axis Measurement: Supplies the voltage. Y axis Measurement: OPEN state. Pen Pressure Measurement: Supplies the voltage. Temperature/VBAT/IN1/IN2 Measurement: OPEN state. Power-down State: OPEN state. Touch Screen Y- plate Voltage Supply Pin Y axis Measurement: Supplies the voltage. X axis Measurement: OPEN state. Pen Pressure Measurement: This pin is the input to the A/D converter at Z2 measurement. Temperature/VBAT/IN1/IN2 Measurement: OPEN state. Power-down State: connected to GND. Touch Screen Controller Ground Pin Analog Input Pin for Battery Monitor Voltage Reference Input/Output Outputs 2.5V at PMVREF bit = "1". Auxiliary 1 Analog Input Pin Auxiliary 3 Analog Input Pin / Current Output Pin for Temperature Sensor Pen Interrupt Output Pin This pin should be pulled up via a 100k resistor. SYNC Signal Input Pin for ADC of Touch Screen Controller No Connect Pin No internal bonding. This pin should be connected to the ground. REV 0.6 -9- 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Handling of Unused Pin The unused I/O pins should be processed appropriately as below. Classification Pin Name MIN, MOUT2, MUTET, SPP, SPN, HPR, HPL, MOUT-, MOUT+, AIN, MICOUT, MDT/RIN, MPE/LIN, EXT/MIC+, INT/MIC-, MPI, AUXIN-, AUXIN+, BEEP/IN2, XP, YP, XN, YN, VBAT, IN1, IOUT, INTN HDT XTO Setting These pins should be open. Analog Digital This pin should be connected to AVSS. This pin should be open. REV 0.6 - 10 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] ABSOLUTE MAXIMUM RATINGS (AVSS, DVSS (DVSS1 & DVSS2), HVSS, TSVSS=0V; Note 1) Parameter Symbol min Power Supplies: Analog AVDD -0.3 Digital (DVDD1 & DVDD2) DVDD -0.3 Headphone-Amp / Speaker-Amp HVDD -0.3 Touch Screen Controller TSVDD -0.3 |AVSS - DVSS| (Note 2) GND1 |AVSS - HVSS| (Note 2) GND2 |AVSS - TSVSS| (Note 2) GND3 Input Current, Any Pin Except Supplies IIN Analog Input Voltage VINA -0.3 Digital Input Voltage VIND -0.3 Touch Screen Controller Input Voltage VINTS -0.3 Touch Screen Drive Current IOUTDRV Ambient Temperature (powered applied) Ta -30 Storage Temperature Tstg -65 max 6.0 6.0 6.0 6.0 0.3 0.3 0.3 10 AVDD+0.3 DVDD+0.3 TSVDD+0.3 50 85 150 Units V V V V V V V mA V V V mA C C Note 1. All voltages with respect to ground. Note 2. AVSS, DVSS (DVSS1 & DVSS2), HVSS and TSVSS must be connected to the same analog ground plane. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AVSS, DVSS (DVSS1 & DVSS2), HVSS, TSVSS=0V; Note 1) Parameter Symbol min typ Power Supplies: Analog AVDD 2.7 3.3 (Note 3) Digital (DVDD1 & DVDD2) DVDD 2.7 3.3 HP / SPK-Amp HVDD 2.7 3.3 Touch Screen Controller TSVDD 2.7 3.3 max 3.6 AVDD 3.6 3.6 Units V V V V Note 1. All voltages with respect to ground. Note 3. The power up sequence between AVDD, DVDD, HVDD and TSVDD is not critical. When the voltage difference among AVDD, DVDD, HVDD and TSVDD is larger than 0.3V, the power supply current at power down mode increases (see Note 22). When the power supplies are partially powered OFF, the AK4650 must be reset by bringing PDN pin "L" after these power supplies are powered ON again. DVDD1 and DVDD2 should be same voltage. * AKM assumes no responsibility for the usage beyond the conditions in this datasheet. REV 0.6 - 11 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] ANALOG CHARACTERISTICS (Audio Block) (Ta=25C; AVDD, DVDD, HVDD, TSVDD=3.3V; AVSS=DVSS=HVSS=TSVSS=0V; fs=48kHz; Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz 20kHz; unless otherwise specified) Parameter min typ max MIC Amplifier: INT, EXT pins, MDIF bit = "0" (Single-ended input) Input Resistance TBD 30 TBD Gain MGAIN bit = "0" 0 MGAIN bit = "1" +20 MIC Amplifier: MIC+, MIC- pins, MDIF bit = "1" (Full-differential input), MGAIN bit = "1" (+20dB) Maximum Input Voltage (Note 4) 0.099 MIC Power Supply: MPI, MPE pins Output Voltage TBD 2.2 TBD Load Resistance 2 Load Capacitance 30 Mic Detection: MDT pin Comparator Voltage Level TBD 0.18 TBD Internal pull down Resistance 250 500 750 Input PGA Characteristics: AIN pin Input Resistance (Note 5) TBD 10 TBD Step Size TBD 0.5 TBD Gain Control Range (ALC1 bit = "0") max: IPGA6-0 bits = "3FH" +27.5 min: IPGA6-0 bits = "00H" -8 ADC Analog Input Characteristics: MIC Gain=+20dB, IPGA=0dB, ALC1=OFF, MIC IPGA ADC Resolution 16 Input Voltage (Note 6) TBD 0.198 TBD S/(N+D) TBD 75 (-1dBFS) D-Range TBD 83 (-60dBFS, A-weighted) S/N (A-weighted) TBD 83 DAC Characteristics: Resolution 16 Mono Line Output Characteristics: RL=20k, DAC MOUT+/MOUT- pins, MOGN2-0 bits = +6dB Output Voltage (Note 7) TBD 3.96 TBD S/(N+D) TBD 85 (-3dBFS) S/N (A-weighted) TBD 95 Load Resistance 20 Load Capacitance 30 Step Size TBD 3 TBD Gain Control Range max: MOGN2-0 bits = "111" +6 min: MOGN2-0 bits = "000" -15 Units k dB dB Vpp V k pF V k k dB dB dB Bits Vpp dB dB dB Bits Vpp dB dB k pF dB dB dB Note 4. Maximum input voltage of MIC+ and MIC- pins are proportional to AVDD voltage. Vin = 0.03 x AVDD(typ). Note 5. When IPGA Gain is changed, this typical value changes between 8k and 11k. Note 6. Input voltage is proportional to AVDD voltage. Vin = 0.06 x AVDD. Note 7. Output voltage is proportional to AVDD voltage. Vout = 1.2 x AVDD(typ)@MOGN2-0 bits = "111" at full-differential output. Vout = 0.6 x AVDD(typ)@MOGN2-0 bits = "111" at single-ended Output. REV 0.6 - 12 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Parameter min typ max Units Headphone-Amp Characteristics: RL=16, DAC HPL/HPR pins, DATT=0dB Output Voltage (Note 8) 0dBFS Input 0.82 Vrms TBD 0.41 TBD Vrms -6dBFS Input S/(N+D) 0dBFS Input 50 dB TBD 60 dB -6dBFS Input S/N (A-weighted) TBD 90 dB Interchannel Isolation TBD 85 dB Interchannel Gain Mismatch 0.1 TBD dB Load Resistance 16 Load Capacitance (Note 9) 300 pF Headphone Detection: HDT pin Comparator Voltage Level (Note 10) 0.99 2.31 V Internal pull down Resistance TBD 100 TBD k Speaker-Amp Characteristics: RL=8, BTL, DAC MOUT2 pin MIN pin SPP/SPN pins, ALC2=OFF Output Voltage (Note 11) 1.55 Vrms -2.5dBFS Input TBD 0.94 TBD Vrms -7.5dBFS Input S/(N+D) 20 dB -2.5dBFS Input TBD 55 dB -7.5dBFS Input S/N (A-weighted) TBD 90 dB Load Resistance 8 Load Capacitance 30 pF Mono Output: DAC MIX MOUT2 pin Output Voltage (Note 12) 1.98 Vpp Load Resistance (Note 13) 30 k Load Capacitance (Note 9, Note 13) 20 pF MIN pin Mono Input: Maximum Input Voltage (Note 14) 1.98 Vpp Input Resistance (Note 15) TBD 24 TBD k BEEP Input: BEEP pin, External input resistance = 20k Maximum Input Voltage (Note 16) 1.98 Vpp Feedback Resistance TBD 20 TBD k Output Voltage (0.8Vpp input) TBD 0.09 TBD Vpp BEEP pin HPL/HPR pins TBD 3.01 TBD Vpp BEEP pin SPP/SPN pins, ALC2 bit = "0" Note 8. Output voltage is proportional to AVDD voltage. Vout = 0.12 x AVDD Vrms(typ)@-6dBFS. Note 9. When the output pin drives a capacitive load, a resistor should be added in series between the output pin and capacitive load. Note 10. Comparator Voltage Level is proportional to HVDD voltage. Vth = 0.3 x HVDD(min), 0.7 x HVDD(max). Note 11. Output voltage is proportional to HVDD voltage. Vout = 0.28 x AVDD Vrms(typ)@-6dBFS at Full-differential output. Note 12. Output Voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD(typ). Note 13. These values do not include the input resistance or capacitance of the MIN pin. Note 14. Maximum Input Voltage is proportional to AVDD voltage. Vin = 0.6 x AVDD(typ). Note 15. When ALC2 Gain is changed, this typical value changes between 22k and 26k. Note 16. Maximum Input Voltage depends on AVDD voltage, internal feedback resistance (Rf) and external input resistance (Ri). Vin = 0.6 x AVDD x Ri / Rf (typ). REV 0.6 - 13 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Parameter Line Input: LIN, RIN pins Maximum Input Voltage (Note 17) Input Resistance Step Size Gain Control Range max: GL4-0 bits = "00H" min: GL4-0 bits = "1FH" AUX Input: AUXIN+, AUXIN- pins Maximum Input Voltage (Note 18) Input Resistance Step Size Gain Control Range max: GN4-0 bits = "00H" min: GN4-0 bits = "1FH" Power Supplies: Power Up (RESETN pin = "H") All Circuit Power-up: AVDD+DVDD (Note 19) HVDD: HP-AMP Normal Operation No Output (Note 20) HVDD: SPK-AMP Normal Operation No Output (Note 21) TSVDD Power Down (RESETN pin = "L") (Note 22) AVDD+DVDD+HVDD+TSVDD min TBD TBD TBD TBD - typ 1.98 40 1.5 +12 -34.5 1.98 40 1.5 +12 -34.5 max TBD TBD TBD TBD - Units Vpp k dB dB dB Vpp k dB dB dB - 14 2.5 7 0.2 - TBD TBD TBD TBD TBD mA mA mA mA A Note 17. Maximum Input Voltage is proportional to AVDD voltage. Vin = 0.6 x AVDD(typ). Note 18. Maximum Input Voltage is proportional to AVDD voltage. Vin = (AUXIN+) - (AUXIN-) = 0.6 x AVDD(typ). Note 19. PR0-6 bits = all "0", PMMIC=PMMO=PMSPK=PMHPL=PMHPR=PMBPM=PMAUX= "1". AVDD=10mA (typ.), DVDD=4mA (typ.). Note 20. PR0-6 bits = all "0", PMMIC=PMMO=PMHPL=PMHPR=PMBPM=PMAUX= "1", PMSPK= "0". Note 21. PR0-6 bits = all "0", PMMIC=PMMO=PMSPK=PMBPM=PMAUX= "1", PMHPL=PMHPR= "0". Note 22. All digital input pins are fixed to DVDD or DVSS. When the voltage difference among AVDD, DVDD, HVDD and TSVDD is larger than 0.3V, the power supply current at power down mode increases. REV 0.6 - 14 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] ANALOG CHARACTERISTICS (TSC Block) (Ta=25C; AVDD, DVDD, HVDD, TSVDD=3.3V; AVSS=DVSS=HVSS=TSVSS=0V; External Vref=2.5V, unless otherwise specified) fs=96kHz Parameter min typ max Units ADC for Touch Screen Resolution 12 Bits No Missing Codes 11 12 Bits LSB Integral Linearity Error 5 LSB DNL 2 Analog Input Voltage Range 0 VREF V LSB Offset Error 6 Gain Error LSB 4 Touch Screen Driver 5 X+, Y+, RL=300 5 X-, Y-, RL=300 PSRR (10KHz 100mVpp) 70 dB Reference Output Internal Reference 2.45 2.50 2.55 V Drift 30 ppm/C Load Capacitance 0.1 F Reference Input Input Voltage Range TSVDD V Input Impedance TBD 196 k Battery Monitor Input Voltage Range 5.0 V Input Impedance (Battery Measure Mode) 5 10 k % Accuracy (Note 23) 2 Temperature Measurement Temperature Range 85 -30 C Resolution (Note 24) 1.6 C Accuracy (Note 25) 3 C Note 23. Accuracy is the difference between the output code when 5 volts is input to the VBAT pin and the "ideal" code at 1.25 volts. Note 24. "Ideal" value derived from theory Note 25. Accuracy is defined as the difference between the voltage measured by two current sources, and the ideal voltage derived from theory at specific temperatures. REV 0.6 - 15 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] FILTER CHARACTERISTICS (Ta=25C; AVDD, HVDD, DVDD, TSVDD=2.7 3.6V; fs=48kHz; DEM=OFF) Parameter Symbol min typ ADC Digital Filter (Decimation LPF): PB 0 Passband (Note 26) 0.1dB -1.0dB 21.8 -3.0dB 23.0 Stopband SB 29.4 Passband Ripple PR Stopband Attenuation SA 65 Group Delay (Note 27) GD 17.0 0 Group Delay Distortion GD ADC Digital Filter (HPF): Frequency Response (Note 26) -3.0dB FR 1.0 6.5 -0.1dB DAC Digital Filter: Passband (Note 27) PB 0 0.1dB 24.0 -6.0dB Stopband SB 25.2 Passband Ripple PR Stopband Attenuation SA 59 Group Delay (Note 27) GD 16.8 DAC Digital Filter + SCF: FR Frequency Response: 0 20.0kHz 1.0 BOOST Filter: (Note 28) Frequency Response MIN 20Hz FR 5.80 100Hz 3.17 1kHz 0.03 MID FR 20Hz 10.85 100Hz 7.23 1kHz 0.18 MAX 20Hz FR 16.14 100Hz 11.05 1kHz 0.47 max 18.9 0.1 21.3 0.01 - Units kHz kHz kHz kHz dB dB 1/fs s Hz Hz kHz kHz kHz dB dB 1/fs dB dB dB dB dB dB dB dB dB dB Note 26. The passband and stopband frequencies scale with fs (system sampling rate). For example, ADC is PB=0.454 x fs (@-1.0dB). The reference frequency of these responses is 1kHz. Note 27. The calculated delay time caused by digital filtering. This time is from the input of analog signal to setting of the 16-bit data of both channels from the input register to the output register of the ADC. This time includes the group delay of the HPF. For the DAC, this time is from setting the 16-bit data of both channels from the input register to the output of analog signal. Note 28. These frequency responses scale with fs. If a high-level and low frequency signal is input, the analog output clips to the full-scale. REV 0.6 - 16 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] DC CHARACTERISTICS (Ta=25C; AVDD, HVDD, DVDD, TSVDD=2.7 3.6V) Parameter Symbol min High-Level Input Voltage VIH 80%DVDD Low-Level Input Voltage VIL Input Voltage at AC Coupling (Note 29) VAC 50%DVDD High-Level Output Voltage VOH (Iout=-400A) DVDD-0.4 Low-Level Output Voltage VOL (Iout=400A) Input Leakage Current Iin Tri-state Leakage Current (TSC block) All pins except for XP, YP, XN, YN pins IOLK -10 XP, YP, XN, YN pins IOLK -50 VOLP INTN "L" level output voltage (100k Pull-Up) Note 29. The external clock is input to MCKI pin via AC coupled capacitor. typ - max 20%DVDD 0.4 10 +10 +50 0.8 Units V V V V V A A A V REV 0.6 - 17 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] SWITCHING CHARACTERISTICS (Ta=25C; AVDD, HVDD, DVDD, TSVDD=2.7 3.6V; CL=25pF) Parameter Symbol min Master Clock Timing Frequency PLL1 pin = "L", PLL0 pin = "L" Fmclk PLL1 pin = "H", PLL0 pin = "L" Fmclk PLL1 pin = "H", PLL0 pin= "H" Fmclk Duty Cycle Dmclk 40 AC link Interface Timing BITCLK frequency Fbclk BITCLK clock Period (Tbclk=1/Fbclk) Tbclk BIT_BLK low pulse width Tclk_low 36 BIT_BLK low pulse width Tclk_high 36 BITCLK rise time Trise_clk BITCLK fall time Tfall_clk SYNC frequency Fsync SYNC low pulse width Tsync_low SYNC high pulse width SYNC rise time SYNC fall time Setup time (SYNC, SDATAOUT) Hold time (SYNC, SDATAOUT) SDATAIN delay time from BITCLK rising edge SDATAIN rise time SDATAIN fall time SDATAOUT rise time SDATAOUT fall time Cold Reset (SDATAOUT = "L", SYNC = "L") RESETN active low pulse width RESETN inactive to BITCLK delay PLL1 pin = "L" (External clock) PLL1 pin = "L" (X'tal oscillator) PLL1 pin = "H", PLL0 pin = "L" PLL1 pin = "H", PLL0 pin = "H" Warm Reset Timing SYNC active high pulse width SYNC inactive to BITCLK delay PLL1 pin = "L" (External clock) PLL1 pin = "L" (X'tal oscillator) PLL1 pin = "H", PLL0 pin = "L" PLL1 pin = "H", PLL0 pin = "H" AC-link Low Power Mode Timing End of Slot 2 to BITCLK, SDATAIN Low Activate Test Mode Timing Setup to trailing edge of RESETN Hold from RESETN rising edge Rising edge of RESETN to Hi-Z Falling edge of RESETN to "L" Tsync_high Trise_sync Tfall_sync Tsetup Thold Tdelay Trise_din Tfall_din Trise_dout Tfall_dout Trst_low Trst2clk Trst2clk Trst2clk Trst2clk Tsync_high 10 25 1.0 1.0 typ max Units 24.576 3.6864 12 12.288 81.38 40.7 40.7 48 19.5 (240 cycle) 1.3 (16 cycle) 42 0.5 9.5 3.2 1.3 (16 cycle) 42 0.5 9.5 3.2 - 60 45 45 6 6 6 6 15 6 6 6 6 - MHz MHz MHz % MHz ns ns ns ns ns kHz s (Tbclk) s (Tbclk) ns ns ns ns ns ns ns ns ns s s ms ms ms s (Tbclk) s ms ms ms s ns ns ns ns Trst2clk Tsync2clk Tsync2clk Tsync2clk Ts2_pdwn Tsetup2rst Thold2rst Toff Tlow 15.0 100 - 1.0 50 50 REV 0.6 - 18 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Timing Diagram 1/Fmclk VIH VIL Tmclkh Tmclkl Dmclk = Tmclkh x Fmclk x 100 = Tmclkl x Fmclk x 100 MCKI Figure 3. Master Clock Timing Tbclk = 1/Fbclk Tclk_high BITCLK 50%DVDD Tclk_low Figure 4. BITCLK Timing Tsync_high SYNC Tsync_low VIH VIL 1/Fsync Figure 5. SYNC Timing Tdelay BITCLK Tsetup VIH VIL SDATAIN Thold SDATAOUT, SYNC VIH VIL VIH VIL Figure 6. Setup and Hold Timing Trise_clk BITCLK Tfall_clk 90%DVDD 10%DVDD Trise_din SDATAIN Tfall_din 90%DVDD 10%DVDD Trise_sync SYNC Tfall_sync 90%DVDD 10%DVDD Trise_dout SDATAOUT Tfall_dout 90%DVDD 10%DVDD Figure 7. Signal Rise and Fall Times (25pF external load; between 10%DVDD and 90%DVDD) REV 0.6 - 19 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Trst_low RESET# Trst2clk VIL SDATAOUT= "L" SYNC= "L" BITCLK Figure 8. Cold Reset Timing Tsync_high SYNC Tsync2clk VIH BITCLK Figure 9. Warm Reset Timing Slot BITCLK SDATAOUT Slot Ts2_pdwn Write to 0x26 Data PR4=1 Don't care SDATAIN Figure 10. AC-link Low Power Mode Timing RESET# VIH VIL VIH SDATAOUT SDATAIN BITCLK Tsetup2rst Thold2rst HI-Z VIL Tlow Toff Figure 11. Activate Test Mode Timing REV 0.6 - 20 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] OPERATION OVERVIEW Master Clock Source The AK4650 requires a master clock (MCLK). This master clock is input to the AK4650 by the following three methods: (1) Connect a X'tal oscillator between XTI and XTO pins. (2) Input an external CMOS-level clock to the XTI pin. (3) Input an external clock whose amplitude is greater than 50%DVDD to the XTI pin with AC coupling. When using a X'tal oscillator, there should be capacitors between XTI/XTO pins and DVSS (Figure 12). Status PR5 bit Oscillator ON 0 Oscillator OFF 1 (Figure 13) Clock is input to MCKI pin. 0 MCKI pin is fixed to "L". 1 MCKI pin is fixed to "H". 1 MCKI pin is Hi-Z 1 External Clock Direct Input (Figure 14) Clock is input to MCKI pin. 0 (PLL1 pin = "H") MCKI pin is fixed to "L". 0 MCKI pin is fixed to "H". 0 MCKI pin is Hi-Z 0 AC Coupling Input (Figure 15) Clock is input to MCKI pin. 0 (PLL1 pin = "L") Clock isn't input to MCKI pin. 1 Table 1. Master Clock Status by PR5 bit and MCKPD bit (Figure 12) (1) X'tal Oscillator (PLL1 pin = "L") Master Clock X'tal Oscillator (PLL1 pin = "L") External Clock Direct Input (PLL1 pin = "L") MCKPD bit 0 1 0 0/1 0 1 0 0/1 0 1 0 1 XTI MCKPD = "0" C PR5 = "0" 25k (typ) C PLL1 = "L" PLL1 = "L" XTO AK4650 Figure 12. X'tal mode Note 30. The capacitor values depend on the X'tal oscillator used. (C : typ. 10 30pF) REV 0.6 - 21 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] (2) External Clock Direct Input (2-1) PLL1 pin = "L" MCKI External Clock MCKPD = "0" PR5 = "0" 25k (typ) PLL1 = "L" PLL1 = "L" XTO AK4650 Figure 13. External Clock mode (PLL1 pin = "L", Input : CMOS Level) Note 31. This clock level must not exceed DVDD level. (2-2) PLL1 pin = "H" MCKI External Clock MCKPD = "0" PR5 = "0" 25k (typ) PLL1 = "H" PLL1 = "H" PLL0 AK4650 Figure 14. External Clock mode (PLL1 pin = "H", Input : CMOS Level) Note 32. This clock level must not exceed DVDD level. (3) AC Coupling Input (PLL1 pin = "L") C External Clock MCKI MCKPD = "0" PR5 = "0" 25k (typ) PLL1 = "L" PLL1 = "L" XTO AK4650 Figure 15. External Clock mode (Input : 50%DVDD) Note 33. This clock level must not exceed DVDD level. (C : 0.1F) REV 0.6 - 22 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] System Clock A fully integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL1-0 pins (Table 2). When the external master clock is used, the PLL should be powered-up after the external master clock is input. It takes 0.5ms(typ) for X'tal oscillator to be stable after PR5 bit = "0" which depends on the X'tal. The PLL needs 9ms lock time, whenever the sampling frequency changes or the PLL is powered-up (VRA bit = "0" "1"). When the clock input to MCKI pin stops during normal operation of AC-Link (PR4 = PR5 bits = "0"), the internal PLL continues to oscillate (a few MHz), and BITCLK output goes to "L" (see Table 3). MCLK and SYNC must be present whenever the ADC or DAC is operating (PR0 = PR1 = PR3 = PR4 = PR5 bits = "0"). If these clocks are not provided, the AK4650 may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not present, the ADC and DAC must be placed in the power-down mode by setting PR0-6 bits. PLL1 pin PLL0 pin MCKI L 24.576MHz L H Reserved L 3.6864MHz H H 12MHz Table 2. MCKI Input Frequency Power down Refer to Table 1 "L" Fixed to "L" or "H" externally Table 3. Clock Operation PLL Unlock Frequency set by PLL1-0 pins (Refer to Table 2) "L" Input or Fixed to "L" or "H" externally MCKI pin BITCLK pin SYNC pin Power up Frequency set by PLL1-0 pins (Refer to Table 2) 12.288MHz Output Input REV 0.6 - 23 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Audio Sample Rate Sample Rate for DAC and ADC is controlled by register 2CH and 32H, respectively. 16bit data in D15(MSB) to D0 show unsigned value from 0 to 65535, representing the exact sampling frequency in Hz. These sample rate setting is done at VRA bit = "1" of Extended Audio Status and Control Register(2Ah). Sample Rate (kHz) Data in D15 - D0 8.0 1F40H 11.025 2B11H 16.0 3E80H 22.05 5622H 24.0 5DC0H 32.0 7D00H 44.1 AC44H 48.0 BB80H Table 4. Audio Sample Rate The AK4650 supports these discrete frequencies. When any other codes is written in this register, the AK4650 operates at the sampling rate rounded to the closest one in Table 4 by decoding only D15-12 bits. If D15-12 = 5H, the AK4650 operates at 22.05kHz or 24kHz when D11 = "0" or "1", respectively (Table 5). D15 - D12 0H,1H 2H 3H 4H D11 Sample Rate (kHz) x 8.0 x 11.025 x 16.0 x 22.05 0 22.05 5H 1 24.0 6H x 24.0 7H,8H x 32.0 9H,AH x 44.1 BH-FH x 48.0 Table 5. Audio Sample Rate (x: Don't care) At VRA bit = "0", 2CH and 32H are fixed to "BB80H" and cannot be written. When VRA bit is set to "0", 2CH and 32H register are set to "BB80H" automatically. And the change of sample rate will be executed on the fly. REV 0.6 - 24 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Power Management Power management of each block is controlled via 26H and 60H register. PR0 = "1" PD PU PU PU VRA PU PMHPL/R PMSPK PMMIC PMLIN PMAUX PMMO PMBPM PM12AD PR1 = "1" PU PD PU PU VRA PU PMHPL/R PMSPK PMMIC PMLIN PMAUX PMMO PMBPM PM12AD PR2 = "1" PR3 = "1" PU PD PU PD PU PD PU PU VRA PD PU PU(Note 34) PD PD PD PD PD PD PD PD PD PD PD PD PD PD PM12AD PD Table 6. Power Management PR4 = "1" PD PD PU PU VRA PD PMHPL/R PMSPK PMMIC PMLIN PMAUX PMMO PMBPM PM12AD PR5 = "1" PD PD PU PD PD PD PMHPL/R PMSPK PMMIC PMLIN PMAUX PMMO PMBPM PM12AD PR6 = "1" PU PU PU PU VRA PU PD PMSPK PMMIC PMLIN PMAUX PMMO PMBPM PM12AD ADC DAC VCM XTL PLL AC-Link HP SPK MIC Line In AUXIN Mono Out BEEP TSC PD: Power Down PU: Power Up PM***: depends on PM*** bit. VRA VRA bit = "1": PLL Power Up VRA bit = "0": PLL Power Down Note 34. When PLL1 pin = "H"(MCKI=3.6864MHz or 12MHz), AC-Link is powered-down by PR3 bit = "1". Digital High Pass Filter The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.0Hz (@fs=48kHz) and scales with sampling rate (fs). REV 0.6 - 25 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] MIC Input AK4650 ATTM bit ATT MICM bit MOUT+/- INT pin MDIF bit MGAIN bit MSEL bit +20dB/0dB IPGA with ALC ALC1 bit IPGA5-0 bits ATTS2-0 bits MICL bit ATT HP, SP MICAD bit ADC EXT pin MICOUT pin AIN pin Figure 16. Microphone Input The AK4650 has the following functions for Mic Input. (1) 2 Inputs Selector. The switch configure is controlled by MDIF and MSEL bits (Table 9). (2) 1st MIC Amplifier with +20dB gain, The gain can be selected ON/OFF by MGAIN bit (Table 10). (3) IPGA with ALC. This volume is controlled by IPGA5-0 bits as Table 14. (4) Attenuator for stereo mixer. The volume is controlled by ATTS2-0 bits as Table 7. (5) Attenuator for mono mixer. The attenuator level is 4dB and the ON/OFF is controlled by ATTM bit (Table 8). ATTS2-0 Attenuation STEP 0H -6dB 1H -9dB Default 2H -12dB 3H -15dB 3dB 4H -18dB 5H -21dB 6H -24dB 7H -27dB Table 7. Attenuator Table (IPGA Stereo Mixer) ATTM Attenuation 0 0dB Default 1 -4dB Table 8. Attenuator Table (IPGA Mono Mixer) REV 0.6 - 26 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] MIC Input Selector AK4650 has mic input selector in front of mic amp. MSEL bit selects internal or external mic (Figure 17). When MDIF bit = "1", INT and EXT pins become MIC- and MIC+ pins, respectively, and differential input is available (Figure 18). MDIF bit MSEL bit Selector 0 INT Default 0 1 EXT 1 x Differential Table 9. MIC Input Selector (x: Don't care) MPE pin MPI pin AK4650 INT pin MIC-Amp EXT pin MDT pin DTMIC bit 500k 0.2V(typ) Figure 17. MIC Input (MDIF bit = "0": Single-ended Input) AK4650 MPI pin MIC- pin MIC+ pin MIC-Amp Figure 18. MIC Input (MDIF bit = "1": Differential Input) Note 35. In case of differential input, MGAIN bit should be set to "1". Maximum input voltage of each input pin is | (MIC+) - (MIC-) | = 0.198Vpp(typ)@AVDD=3.3V. REV 0.6 - 27 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] MIC Gain Amplifier The AK4650 has a Gain Amplifier for Microphone input. The gain is 0dB or +20dB, selected by the MGAIN bit. The typical input impedance is 30k. MGAIN bit Input Gain 0 0dB Default 1 +20dB Table 10. MIC Input Gain MIC Power The MPI and MPE pins supply power for the Microphone. These output voltages are 2.2V (typ) and load resistance is 2k (min). MPWRI and MPWRE bits control output from MPI and MPE pins, respectively. When LNMP bit = "1", MPE pin becomes LIN pin. MPWRI bit MPI pin x Hi-Z Default 0 Hi-Z 1 1 Output Table 11. Internal Microphone Power Supply (x: Don't care) MPWRE bit MPE pin x Hi-Z Default 0 Hi-Z 1 1 Output Table 12. External Microphone Power Supply (x: Don't care) PMMIC bit 0 PMMIC bit 0 MIC Detection Function The AK4650 includes the detection function of microphone. Example of the detection of external microphone. (1) MPWRE bit = "1". (2) MPE drives external microphone. (3) DTMIC bit is set by Table 13. Input Level of MDT DTMIC bit External microphone > 0.247V 1 Connect < 0.165V 0 Disconnect Table 13. Microphone detection result When RNMD bit = "1", MDT pin becomes RIN pin. REV 0.6 - 28 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Manual Mode The AK4650 becomes a manual mode at ALC1 bit = "0". The mode is used in the case shown below. (1) After exiting reset state, set up the registers for the ALC1 operation (ZTM1-0, LMTH and etc) (2) When the registers for the ALC1 operation (Limiter period, Recovery period and etc) are changed. For example; When the change of the sampling frequency. (3) When IPGA is used as a manual volume. When writing to the IPGA5-0 bits continually, the control register should be written by an interval more than zero crossing timeout. MICMT IPGA5-0 GAIN (dB) STEP 3FH +27.5 3EH +27.0 0.5dB : : 09H +0.5 08H +0.0 07H -1.0 06H -2.0 1.0dB : : 01H -7.0 00H -8.0 x MUTE Table 14. IPGA Volume (x: Don't care) 0 Default 1 REV 0.6 - 29 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] MIC-ALC Operation The ALC (Automatic Level Control) of MIC input is done by ALC1 block when ALC1 bit is "1". (1) ALC1 Limiter Operation When the ALC1 limiter is enabled, and IPGA output exceeds the ALC1 limiter detection level (LMTH bit: Table 15), the IPGA value is attenuated by the amount defined in the ALC1 limiter ATT step (LMAT1-0 bits: Table 16) automatically. When the ZELMN bit = "1", the timeout period is set by the LTM1-0 bits (Table 17). The operation for attenuation is done continuously until the IPGA output signal level becomes LMTH or less. If the ALC1 bit does not change into "0" after completing the attenuation, the attenuation operation repeats while the IPGA output signal level equals or exceeds LMTH. When the ZELMN bit = "0", the timeout period is set by the ZTM1-0 bits (Table 18). This enables the zero-crossing attenuation function so that the IPGA value is attenuated at the zero-detect points of the waveform. LMTH 0 1 ALC1 Limiter Detection Level ALC1 Recovery Waiting Counter Reset Level ADC Input -6.0dBFS -6.0dBFS > ADC Input -8.0dBFS ADC Input -4.0dBFS -4.0dBFS > ADC Input -6.0dBFS Table 15. ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level Default LMAT1 LMAT0 ATT STEP 0 0 0.5dB Default 0 1 1.0dB 1 0 1.5dB 1 1 2.0dB Table 16. ALC1 Limiter ATT Step Setting Note: When IPGA gain is 0dB or less, ALC1 limiter ATT step is fixed to 1 regardless as LMAT1-0 bits. LTM1 ALC1 Limiter Operation Period 8kHz 16kHz 44.1kHz 0 0 0.5/fs Default 63s 31s 11s 0 1 1/fs 125s 63s 23s 1 0 2/fs 250s 125s 45s 1 1 4/fs 500s 250s 91s Table 17. ALC1 Limiter Operation Period at zero crossing disable (ZELMN bit = "1") LTM0 ZTM0 0 1 0 1 Zero Crossing Timeout Period 8kHz 16kHz 128/fs 16ms 8ms 256/fs 32ms 16ms 512/fs 64ms 32ms 1024/fs 128ms 64ms Table 18. Zero Crossing Timeout Period ZTM1 0 0 1 1 44.1kHz 2.9ms 5.8ms 11.6ms 23.2ms Default REV 0.6 - 30 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] (2) ALC1 Recovery Operation The ALC1 recovery refers to the amount of time that the AK4650 will allow a signal to exceed a predetermined limiting value prior to enabling the limiting function. The ALC1 recovery operation uses the WTM1-0 bits to define the wait period used after completing an ALC1 limiter operation (Table 19). If the input signal does not exceed the "ALC1 Recovery Waiting Counter Reset Level" (LMTH: Table 15), the ALC1 recovery operation starts. The IPGA value increases automatically by the recovery gain step (RGAIN bit: Table 20) with zero crossing operation (timeout is set by ZTM1-0: Table 18) during this operation up to the reference level (REF5-0 bit: Table 21). The ALC1 recovery operation is done at a period set by the WTM1-0 bits. Zero crossing is detected during WTM1-0 period, the ALC1 recovery operation waits WTM1-0 period and the next recovery operation starts. During the ALC1 recovery operation, when input signal level exceeds the ALC1 limiter detection level (LMTH), the ALC1 recovery operation changes immediately into an ALC1 limiter operation. In the case of (Recovery waiting counter reset level) (IPGA Output Level) < (Limiter detection level) during the ALC1 recovery operation, the wait timer for the ALC1 recovery operation is reset. Therefore, in the case of (Recovery waiting counter reset level) > (IPGA Output Level), the wait timer for the ALC1 recovery operation starts. The ALC1 operation corresponds to the impulse noise. When the impulse noise is input, the ALC1 recovery operation becomes faster than a normal recovery operation. WTM1 0 0 1 1 WTM0 0 1 0 1 ALC1 Recovery Operation Waiting Period 8kHz 16kHz 44.1kHz 128/fs 16ms 8ms 2.9ms 256/fs 32ms 16ms 5.8ms 512/fs 64ms 32ms 11.6ms 1024/fs 128ms 64ms 23.2ms Table 19. ALC1 Recovery Operation Waiting Period RGAIN GAIN STEP 0 0.5dB Default 1 1.0dB Table 20. ALC1 Recovery Gain Step Setting REF5-0 GAIN (dB) STEP 3DH +26.5 3CH +26.0 : : 0.5dB 2DH +19.0 Default : : 05H +0.5 04H +0.0 03H -1.0 02H -2.0 1.0dB : : 01H -7.0 00H -8.0 Table 21. Setting Reference Value at ALC1 Recovery Operation Default REV 0.6 - 31 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] (3) Example of ALC1 Operation Table 22 shows the examples of the ALC1 setting. In case of this examples, ALC1 operation starts from 0dB. Register Name LMTH LTM1-0 ZELMN ZTM1-0 WTM1-0 REF5-0 IPGA5-0 LMAT1-0 RGAIN ALC1 Comment fs=8kHz Operation -4dBFS Don't use fs=16kHz Operation -4dBFS Don't use Enable 16ms 16ms +27.5dB 0dB 0.5dB 0.5dB Enable fs=44.1kHz Data Operation 1 -4dBFS 00 Don't use 0 10 10 00H 37H 00 0 1 Enable 11.6ms 11.6ms +27.5dB 0dB 0.5dB 0.5dB Enable Limiter detection Level Limiter operation period at ZELMN bit = "1" Limiter zero crossing detection 0 Enable 0 Zero crossing timeout period 00 16ms 01 Recovery waiting period *WTM1-0 bits should be the same 00 16ms 01 data as ZTM1-0 bits Maximum gain at recovery operation 00H +27.5dB 00H Gain of IPGA at ALC1 operation start 37H 0dB 37H Limiter ATT Step 00 0.5dB 00 Recovery GAIN Step 0 0.5dB 0 ALC1 Enable bit 1 Enable 1 Table 22. Example of the ALC1 setting Data 1 00 Data 1 00 The following registers should not be changed during the ALC1 operation. These bits should be changed, after the ALC1 operation is finished by ALC1 bit = "0" or PMMIC bit = "0". * LTM1-0, LMTH, LMAT1-0, WTM1-0, ZTM1-0, RGAIN, REF5-0, ZELMN bits IPGA gain at ALC1 operation start can be changed from the default value of IPGA5-0 bits while PMMIC bit is "1" and ALC1 bit is "0". When ALC1 bit is changed from "1" to "0", IPGA holds the last gain value set by ALC1 operation. Example: Limiter = Zero crossing Enable Recovery Cycle = 16ms @ fs= 8kHz Limiter and Recovery Step = 0.5dB Maximum Gain = +27.5dB Limiter Detection Level = -4dBFS Manual Mode ALC2 bit = "1" (default) (1) Addr=66H, Data=4100H WR (ZTM1-0, WTM1-0, LTM1-0) WR (REF5-0) (2) Addr=64H, Data=0031H WR (IPGA5-0) * The value of IPGA should be the same or smaller than REF's (3) Addr=0EH, Data=0077H WR (ALC1= "1", LMAT1-0, RGAIN, LMTH, ZELMN) (4) Addr=66H, Data=6100H ALC1 Operation Note : WR : Write Figure 19. Registers set-up sequence at ALC1 operation REV 0.6 - 32 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] De-emphasis Filter The AK4650 includes the digital de-emphasis filter (tc = 50/15s) by IIR filter. Setting the DEM1-0 bits enables the de-emphasis filter (Table 23). DEM1 0 0 1 1 DEM0 Mode 0 44.1kHz 1 OFF Default 0 48kHz 1 32kHz Table 23. De-emphasis Control Bass Boost Function The BST1-0 bits control the amount of low frequency boost applied to the DAC output signal (Table 24). If the BST1-0 bits are set to "10" (MID Level), AC-coupling capacitor can be sized down to 47F. If the boosted signal exceeds the full scale, the analog output clips to the full scale. Figure 20 shows the boost frequency response at -20dB signal input. Boost Filter (fs=48kHz) 20 MAX 15 MID Level [dB] 10 MIN 5 0 -5 10 100 Frequency [Hz] 1000 10000 Figure 20. Bass Boost Frequency (fs=48kHz) BST1 0 0 1 1 BST0 Mode 0 OFF 1 MIN 0 MID 1 MAX Table 24. Bass Boost Control Default REV 0.6 - 33 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Digital Attenuator The AK4650 has a channel-independent digital attenuator (128 levels, 0.5dB step, Mute). The attenuation level of each channel can be set by the ATTL/R6-0 bits (Table 25). When the DATTC bit = "1", the ATTL6-0 bits control both Lch and Rch attenuation levels. When the DATTC bit = "0", the ATTL6-0 bits control Lch level and ATTR6-0 bits control Rch level. ATTL/R6-0 Attenuation STEP 00H 0dB 01H -0.5dB 02H -1.0dB 0.5dB : : 7DH -62.5dB 7EH -63.0dB 7FH MUTE (-) Table 25. DATT Attenuation Table Default The ATS bit sets the transition time between set values of ATTL/R6-0 bits as either 531/fs or 128/fs (Table 26). When ATS bit = "0", a soft transition between the set values occurs (531 levels). It takes 531/fs (11ms@fs=48kHz) from 00H(0dB) to 7FH(MUTE). ATT speed 0dB to MUTE 1 step 0 531/fs 4/fs Default 1 128/fs 29/fs Table 26. Transition time between set values of ATTL/R6-0 bits ATS REV 0.6 - 34 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Soft Mute Soft mute operation is performed in the digital domain. When the SMUTE bit goes to "1", the output signal is attenuated by - ("0") during the cycle set by the TM1-0 bits (Table 27). When the SMUTE bit is returned to "0", the mute is cancelled and the output attenuation gradually changes to 0dB during the cycle set of the TM1-0 bits. If the soft mute is cancelled within the cycle set by the TM1-0 bits after starting the operation, the attenuation is discontinued and returned to 0dB. The soft mute is effective for changing the signal source without stopping the signal transmission (Figure 21). The soft mute function is independent of output volume and cascade connected between both functions. SM U T E bit TM 1-0 bit TM 1-0 bit 0dB Attenuation (1) (3) - GD (2) Analog O utput GD Figure 21. Soft Mute Function Note: (1) The output signal is attenuated until - ("0") by the cycle set by the TM1-0 bits. (2) Analog output corresponding to digital input has the group delay (GD). (3) If the soft mute is cancelled within the cycle of setting the TM1-0 bits, the attenuation is discounted and returned to 0dB(the set value). TM1 0 0 1 1 TM0 Cycle 0 1024/fs Default 1 512/fs 0 256/fs 1 128/fs Table 27. Soft Mute Time Setting REV 0.6 - 35 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] AUX Input AK4650 AUXIN+ pin AUXIN- pin AUXAD bit AUXMT, GN4-0 bits Volume ADC HP, SP AUXL bit Figure 22. AUX Input AUX input is a differential input. The AK4650 has a volume for AUX Input. This Volume is controlled by GN3-0 bits as shown in Table 28. The AK4650 register control for GN3-0 does not have function to reduce any pop noise at volume setting change. AUXMT GN4-0 GAIN (dB) STEP 00H +12.0 01H +10.5 02H +9.0 1.5dB : : 08H +0.0 : : 1EH -33.0 1FH -34.5 x MUTE Table 28. AUX Input Gain Setting (x: Don't care) 0 Default 1 REV 0.6 - 36 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Stereo Line Input AK4650 LIN pin HP Lch, SP LNMT, GL4-0 bits Volume RIN pin HP Rch, SP LNMT, GR4-0 bits Volume Figure 23. Stereo Line Input When LNMP bit is "1", MPE pin becomes LIN pin. When RNMD bit is "1", MDT pin becomes RIN pin. LIN/RIN is single-ended input. The AK4650 has a volume for Stereo Line Input. This Volume is controlled by GL4-0 and GR4-0 bits as shown in Table 28. The AK4650 register control for GL4-0 and GR4-0 does not have function to reduce any pop noise at volume setting change. LNMT GL/GR4-0 GAIN (dB) STEP 00H +12.0 01H +10.5 02H +9.0 1.5dB : : 08H +0.0 : : 1EH -33.0 1FH -34.5 x MUTE Table 29. Stereo Line Input Volume Setting (x: Don't care) 0 Default 1 REV 0.6 - 37 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] BEEP Input When the PMBPM bit is set to "1", mono beep input is powered up. And when the BPMHP bit is set to "1", the signal from the BEEP pin is input to Headphone-amp. When the BPMSP bit is set to "1", the signal from the BEEP pin is input to Speaker output. The external resisters Ri adjust the signal level of each BEEP input that are mixed to Headphone and Speaker outputs. The signal from the BEEP pin is mixed to the Headphone-amp through a -20dB gain stage. The signal from the BEEP pin is mixed to the Speaker-amp without gain. The internal feedback resistance is 20k 30%. When BPMT bit is "1", BEEP input is muted. When INBP bit is "1", BEEP pin becomes IN2 pin. AK4650 BPMHP bit -20dB Rf Ri BEEP pin SP BPMSP bit HP Rch HP Lch Figure 24. Block Diagram of BEEP pins (Rf = 20k 30%) REV 0.6 - 38 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] MONO LINE OUTPUT (MOUT+ and MOUT- pins) MICOUT pin AIN pin AK4650 MIC In ATT +20dB/0dB IPGA5-0 bits ATTM bit MICM bit DAMO bit 1/2 ATT+DAC 1/2 MOUT+ pin MOUT- pin MOGN2-0 bits +6dB to -15dB Figure 25. Mono Output Mono mixer mixes signals from MIC In, DAC Lch and Rch. This mixed signal is output from the MOUT+ and MOUT- pins, creating a differential output. Either the MOUT+ or MOUT- pin can be also used as single-ended output. Load resistance is 20k(min). When PMMO bit is "0", mono output is powered-down and MOUT+/- pins become Hi-Z. PMMO 0 1 MOMT x 1 0 Mode MOUT+/MOUT- pin Power-down Hi-Z Mute VCOM Normal operation Normal operation Table 30. Mono Output Setting Default Volume of path from DAC is controlled by ATTL7-0 and ATTR7-0 bits (Table 25). Volume of path from IPGA is controlled by ATTM bit (Table 8). Mono output amp has +6dB to -15dB gain that are set by the MOGN2-0 bits (Table 31). MOGN2-0 0H 1H 2H 3H 4H 5H 6H 7H GAIN (dB) STEP +6.0 +3.0 +0.0 -3.0 3dB -6.0 -9.0 -12.0 -15.0 Table 31. Mono Output Gain Control Default REV 0.6 - 39 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Headphone Output Power supply voltage for the Headphone-amp is supplied from the HVDD pin and centered on the MUTET voltage. The Headphone-amp output load resistance is min.16. When the HPMT bit is "1" at PMHPL=PMHPR= "1", the common voltage rises to HVDD/2. When the HPMT bit is "1", the common voltage of Headphone-amp falls and the outputs (HPL and HPR pins) go to HVSS. A capacitor between the MUTET pin and ground reduces pop noise at power-up/down. It is recommended that the capacitor with small variation of capacitance and low ESR (Equivalent Series Resistance) over all temperature range, since the rise and fall time in Table 32 depend on the capacitance and ESR of the external capacitor at MUTET pin. tr: Rise Time up to HVDD/4 100k x C (typ) tf: Fall Time down to 0V 200k x C (typ) Table 32. Headphone-Amp Rise/Fall Time [Example]: A capacitor between the MUTET pin and ground = 1.0F: Rise Time up to HVDD/4: tr = 100k x 1F = 100ms(typ) Fall Time down to 0V: tf = 200k x 1F = 200ms(typ) When PMHPL and PMHPR bits are "0", the Headphone-amp is powered-down, and the outputs (HPL and HPR pins) go to HVSS. PMHPL/R bit HPMT bit HVDD/2 HVDD/4 tf (3) (4) HPL/R pin tr (1) (2) Figure 26. Power-up/Power-down Timing for Headphone-amp (1) Headphone-amp power-up (PMHPL and PMHPR bits = "1"). The outputs are still HVSS. (2) Headphone-amp common voltage rises up (HPMT bit = "0"). Common voltage of Headphone-amp is rising. This rise time depends on the capacitor value connected with the MUTET pin. The rise time up to HVDD/4 is tr = 100k x C(typ) when the capacitor value on MUTET pin is "C". (3) Headphone-amp common voltage falls down (HPMT bit = "1"). Common voltage of Headphone-amp is falling to HVSS. This fall time depends on the capacitor value connected with the MUTET pin. The fall time down to 0V is tf = 200k x C(typ) when the capacitor value on MUTET pin is "C". (4) Headphone-amp power-down (PMHPL, PMHPR bits = "0"). The outputs are HVSS. If the power supply is switched off or Headphone-amp is powered-down before the common voltage goes to HVSS, some pop noise occurs. REV 0.6 - 40 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] The cut-off frequency of Headphone-amp output depends on the external resistor and capacitor used. Table 33 shows the cut off frequency and the output power for various resistor/capacitor combinations. The Headphone impedance RL is 16. Output powers are shown at HVDD = 2.7, 3.0 and 3.3V. The output voltage of Headphone is 0.6 x AVDD (Vpp). HP-AMP R C Headphone 16 AK4650 Figure 27. External Circuit Example of Headphone R [] 0 6.8 16 Output Power [mW] fc [Hz] fc [Hz] BOOST=OFF BOOST=MIN 2.7V 3.0V 220 45.2 17 27.9 34.5 100 99.5 42 100 69.8 28 13.7 17.0 47 148.5 74 100 49.7 19 7.0 8.6 47 105.8 46 Table 33. Relationship of external circuit, output power and frequency response C [F] 3.3V 41.7 20.5 10.4 REV 0.6 - 41 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Headphone Jack Detection AK4650 HVDD 100k HPDT bit HDT pin DTHPJ bit Headphone Jack Not inserted Inserted Pins 1 and 2 Short Open HDT pin "L" (pulled-down by external 2.2k) "H" (pulled-up by internal 100k) HPL pin 6.8 47u 2.2k 1 2 3 4 5 Headphone Out HPR pin 6.8 47u 2.2k Figure 28. Headphone Jack Detection Headphone jack detection sequence example: (1) HPDT bit = "1". (2) HDT pin is pulled-up to HVDD by 100k. (3) DTHPJ bit indicates whether headphone jack is inserted or not. Headphone jack detection result is reported to DTHPJ bit (Table 34). If HPINT bit is "1", INTN pin becomes "L" when headphone jack is detected. Input Level of HDT DTHPJ bit Headphone Jack < 0.3 x HVDD 0 Not inserted > 0.7 x HVDD 1 Inserted Table 34. Headphone Jack Detection Result When ATSW bit is "1" at PMHPL=PMHPR=PMSPK= "1" and HPMT=SPPS= "0", Headphone-amp and Speaker-amp are automatically powered-up/down according to headphone jack detection result (Table 35, Table 36). DTHPJ PMHPL HPMT HP-Amp PMHPR 0 x x Power Down 0 1 Power Down 1 1 0 Power UP Table 35. Headphone-amp automatic power-down (ATSW bit = "1") SPPS SPK-Amp X Power Down 0 1 Power Save 1 0 Power UP 0 X Power Down 1 1 X Power Save Table 36. Speaker-amp automatic power-save (ATSW bit = "1") PMSPK 0 DTHPJ REV 0.6 - 42 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Speaker Output Mono signal [(L+R)/2] converted from stereo DAC output and BEEP input signal can be output via Speaker-amp which output is BTL. DAC output signal can be input to the Speaker-amp via the ALC2 circuit. This Speaker-amp can output a maximum of 300mW@ALC2 bit = "0" and 200mW@ALC2 bit = "1". ALC2 Po 0 300mW Default 1 200mW Table 37. Speaker-Amp Output Power Speaker blocks (MOUT2, ALC2 and Speaker-amp) can be powered-up/down by controlling the PMSPK bit. When the PMSPK bit is "0", the MOUT2, SPP and SPN pins are placed in a Hi-Z state. When the SPPS bit is "1", the Speaker-amp is power-save-mode. In this mode, the SPP pin is placed in a Hi-Z state and the SPN pin goes to HVDD/2 voltage. And then the Speaker output gradually changes to the HVDD/2 voltage and this mode can reduce pop noise at power-up. When the AK4650 is powered-down, pop noise can be also reduced in power-save-mode. PMSPK 0 1 SPPS x 1 0 Mode SPP pin Power-down Hi-Z Power-save Hi-Z Normal operation Normal operation Table 38. Speaker Output Setting SPN pin Hi-Z HVDD/2 Normal operation Default PMSPK bit SPPS bit SPP pin Hi-Z Hi-Z SPN pin Hi-Z HVDD/2 HVDD/2 Hi-Z Figure 29. Power-up/Power-down Timing for Speaker-amp Mono Output (MOUT2 pin) The mixed Lch/Rch signal of DAC is output from the MOUT2 pin. When the MO2 bit is "0", this output is OFF and the MOUT2 pin is forced to VCOM voltage. The load impedance is 10k (min.). When the PMSPK bit is "0", the Speaker-amp enters power-down-mode and the output is placed in a Hi-Z state. REV 0.6 - 43 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] ALC2 Operation Input resistance of the ALC2 (MIN pin) is 24k (typ) and centered around VCOM voltage. Figure 30 shows input-output relationship at ALC2 operation (0dBV=1Vrms =2.828Vpp). The limiter detection level is proportional to HVDD. The output level is limited by the ALC2 circuit when the Speaker-amp output level exceeds +2dBV@HVDD=3.3V. When a continuous signal of +2dBV or greater is input to the ALC2 circuit, the output level is attenuated by ALC2 operation. The change period of the ALC2 limiter operation is set by the ROTM bit and the attenuation level is 0.5dB/step (Table 39). When the Speaker-amp output level is equal to or lower than 0dBV@HVDD=3.3V, the ALC2 recovery opeation starts. The ALC2 recovery operation uses zero crossings and gains of 1dB/step. The ALC2 recovery operation is done until the output level of the Speaker-amp goes to 0dBV@HVDD=3.3V. The ALC2 maximum gain is +18dB. The ROTM bit sets the ALC2 recovery operation period (Table 39). When the output signal is between +2dBV and 0dBV, the ALC2 limiter or recovery operations are not done. When the PMSPK bit changes from "0" to "1", the initilization cycle (2048/fs = 46.4ms @fs=44.1kHz at ROTM bit = "0", 512/fs = 11.6ms @fs=44.1kHz at the ROTM bit = "1") starts. This fs value is set by Addr=32H (ADC sampling frequence). The ALC2 is disabled during the initilization cycle and the ALC2 starts after completing the initilization cycle. Parameter ALC2 Limiter operation ALC2 Recovery operation Operation Start Level +2dBV 0dBV ROTM bit = "0" 2048/fs = 46.4ms@fs=44.1kHz 2/fs = 45s@fs=44.1kHz Period ROTM bit = "1" 512/fs = 46.4ms@fs=11.025kHz 2/fs = 181s@fs=11.025kHz Zero-crossing Detection Diabled Enabled (Timeout = 2048/fs) ATT/GAIN 0.5dB step 1dB step Table 39. Limiter /Recovery of ALC2 at HVDD=3.3V SPK Out +3.8dBV +2dBV 0dBV (Recovery) (Limitter) (ALC2=OFF) -18dBV -2dBFS -25dBFS -23dBFS 0dBFS DAC In Figure 30. DAC input - Speaker output relationship (HVDD=3.3V, ALC2 bit = "1") REV 0.6 - 44 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Example of Path Microphone Mic In AK4650 Audio CODEC ADC CPU Headphone HP Out HP Amp DAC RF Module Aux In Mono Out Figure 31. MIC recording & Headphone playback Microphone Mic In AK4650 Audio CODEC ADC Side Tone ATT CPU Headphone HP Out HP Amp DAC RF Module Aux In Mono Out Figure 32. Phone Microphone Mic In AK4650 Audio CODEC ADC Side Tone ATT CPU Headphone HP Out HP Amp DAC RF Module Aux In Mono Out Figure 33. Recording/Playback & Phone REV 0.6 - 45 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] A/D Converter for Touch Screen The AK4650 incorporates a 12-bit successive approximation resistor A/D converter for position measurement, temperature, and battery voltage. The architecture is based on capacitive redistribution algorithm, and an internal capacitor array functions as the sample/hold circuit. The A/D converter output is a straight binary format as shown in Table 40: Input Voltage (VREF-1.5LSB) ~ VREF (VREF-2.5LSB) ~ (VREF-1.5LSB) : 0.5LSB ~ 1.5LSB 0 ~ 0.5LSB VREF: (VREF+) - (VREF-) Table 40. Output Code The A/D converter's full scale measurements depend on the input mode. Output Code FFF FFE : 001 000 Analog Inputs Analog input is selected via the A2-0 and SER bits in the control register. If the analog inputs are the X or Y-axis and the SER bit is set to "0"(differential mode), the full scale (VREF) is the differential voltage between the non-inverting terminal and the inverting terminal of the measured axis (e.g. (XP) - (XN)). Analog non-inverting input to A/D converter (AIN) is the non-inverting terminal of the non-measured axis while the inverting input is the inverting terminal of the measured axis. If the SER bit is set to "1" (single-ended mode), the full scale of A/D converter (VREF) is the internal reference voltage, or external reference voltage. Note that the SER bit should be set to "0" if the IN2 pin is selected as analog input; nevertheless, the IN2 pin is actually measured by single-ended mode. SER bit 0 1 Analog Input Type VREF AIN X-axis measurement: XP - XN X-axis measurement: YP - XN Differential Y-axis measurement: YP - YN Y-axis measurement: XP - YN Single-ended VREF - TSVSS AIN - TSVSS Table 41. Analog Input Type, VREF and AIN REV 0.6 - 46 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Pen Position Detection of Touch Screen The selected touch screen position is detected by the voltage measurement of one axis when the voltage is supplied between the two terminals of the other axis. At least two A/D conversions are needed to get the two-dimensional (X/Y axis) position. ON XP ON XP VREF+ AIN+ VREF+ AIN+ ADC VREFAIN- YP ADC VREFAIN- YP XN XN ON YN ON YN a) X-Position Measurement Differential Mode b) Y-Position Measurement Differential Mode Figure 34. Axis Measurement The differential mode is generally more accurate than the single-ended mode for the position detection. Since the full scale of single-ended mode is fixed to the internal (or external) reference voltage, the input voltage may exceed the full-scale reference voltage. This problem does not occur in differential mode. In addition to this, the differential mode is less influenced by power supply voltage variation by the ratio-metric measurement. However, note that the touch screen driver switch is still ON and the current flows even for the A/D conversion time. REV 0.6 - 47 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Pen Pressure Measurement The touch screen pen pressure can be derived from the measurement of the contact resistance between two plates. The contact resistance depends on the size of the depressed area and the pressure. The area of the spot is proportional to the contact resistance. This resistance (Rtouch) can be calculated using two different methods. The first method uses the total resistance of the X-plate sheet. The resistance, Rtouch, is calculated from the results of three conversions, X-position, Z1-Position, and Z2-Position, using the following formula: 1) Total resistance of the X-plate sheet (Rxplate) is known The resistance, Rtouch, is calculated from the results of three conversions, X-position, Z1-Position, and Z2-Position, using the following formula: Xposition 4096 Rtouch = Rxplate x x ( Z2 Z1 -1 ) The second method uses the resistances of both the X-plate and Y-plate. The resistance, Rtouch, is calculated from the results of three conversions, X-position, Y-Position, and Z1-Position, using the following formula: 2) The resistances of both the X-plate and Y-plate (Rxplate, Ryplate) are known The resistance, Rtouch, is calculated from the results of three conversions, X-position, Y-Position, and Z1-Position, using the following formula: Xposition 4096 Rtouch = Rxplate x x ( YP XP 4096 Z1 -1 ) - Ryplate x ( Yposition 1- 4096 ) YP XP touch AK4650 ON AK4650 ON touch VREF+ AIN+ VREF+ AIN+ ADC VREFAIN- ADC VREFAIN- XN XN ON YN ON YN a) Z1-Position Measurement Differential Mode b) Z2-Position Measurement Differential Mode Figure 35. Pen Pressure Measurement REV 0.6 - 48 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Voltage Reference (VREF) The AK4650 has an internal 2.5V voltage reference. This reference can be turned ON when PMVREF = "1", and OFF when PMVREF = "0". This reference is used in the single-ended mode for the battery monitoring, temperature measurement, or for auxiliary input. A 0.1F or larger capacitor should be connected for stable operation of the VREF circuit. Settling time depends on this external capacitance, but 400s or longer time is required if the external capacitance is 0.1F. If an external voltage reference is used, PMVREF bit should be set to "0". Battery Measurement The AK4650 can measure the battery voltage of 5V or less directly while the AK4650 operates at 2.7V to 3.6V. The input voltage is internally divided down by four. When the tracking time is adjusted at battery measurement, the method using ADEXE pin is available. ADEXE1-0 bits select the tracking edge (Table 52). VREF AK4650 Internal VREF VBAT R0 R1=7.5K AINR2=2.5K AIN+ ADC PD1 VREF+ VREF- Enable Figure 36. Battery Monitoring REV 0.6 - 49 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Temperature Measurement Equation <1> describes the forward characteristics of the diode. iD=I0exp(vD/VT) (VT = kT/q) <1> I0: reverse saturation current q : 1.602189 x 10-19 (electron charge) k : 1.38054 x 10-23 (Boltzmann's constant) vD: voltage across diode T: absolute temperature K Since a diode junction voltage is theoretically proportional to the temperature, the ambient temperature can be predicted by measuring this voltage. AK4650 IOUT External Temp. Sensor I 82I TEMP0 TEMP1 Figure 37. Temperature Measurement Since the AK4650 has two different fixed current circuits (Figure 37), the temperature can be measured by using two different methods. The first method needs two conversions, but can derive the temperature directly without knowing the voltage at a specific temperature. From equation <1>, (iD2 / iD1) = exp{(v(NI) - v(I))/VT}, N = (iD2 / iD1) = 82 (ratio of the current) T[C] = (Vbe x q) / (k x ln N) - 273 Vbe = V(I82) - V(I) T[C] = 2.63 x 103 x Vbe - 273 The second method needs only one conversion as the following equation, but requires knowing the junction voltage at the specific temperature. T[K] = (k/q) x vD / ln(iD/I0) <2> REV 0.6 - 50 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Pen Interrupt The AK4650 has pen interrupt function to detect the pen touch. Pen interrupt function is enabled at power-down state. YN pin is connected to GND at the PEN interrupt enabled state. And XP pin is pulled up via an internal resistor (Ri), typically 50k. INTN pulled up via an external resistor, 100k, is also connected to XP pin. If the two plates are touched, the current flows via 100k AK4650 INTN pin EN2 50k EN1 Driver OFF XP pin YN pin Driver ON Figure 38. Pen Interrupt Block Diagram REV 0.6 - 51 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Sequence from AC-Link Power-up to Headphone Output TSC T ouch IN T N S D A T A _ IN SYN C C r y s t a l O c ila t o r M in : 2 0 m s B IT C L K V R A b it( P L L ) T im e r m in :2 5 m s PLL m in :2 0 m s P R 1 b it( D A C ) V R A b it( P L L ) P R 6 b it( H P ) T y p .5 0 m s H P L /R ( N o te ) Note 36. When PR2 = PR3 = PR6 = "0", auto power-up function is selected (ATPU bit = "1") and pen touch is detected, then the AK4650 automatically starts to power-up the headphone-amp by setting PMHPL bit = "1", PMHPR bit = "1" and HPMT bit = "0". Figure 39. Sequence from AC-Link power-up to headphone output REV 0.6 - 52 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Waking up AC-Link 1. AC-Link Power-down The AK4650 controls the AC-link power-up/down by PR4 and PR5 bits. When PR4 bit is "1", BITCLK and SDATAIN go to "L", but X'tal oscillator still operates. When PR5 bit is "1", BITCLK and SDATAIN go to "L", and X'tal oscillator is powered-down. PLL power-up/down is controlled by VRA bit. BITCLK/SDATAIN output X'tal oscillator Stop Normal operation Stop Stop Output Normal operation Table 42. AC-Link Power-down PLL Power Down Power Down Power Down PR4 bit = "1" PR5 bit = "1" VRAbit = "0" 2. AC-Link Power-up The AK4650 supports the AC-link power-up sequence using SDATAIN output in addition to COLD RESET and WARM RESET. In this mode the operation is same as WARM RESET when the AK4650 receives the SYNC signal. CODEC Sleep State Power Down SYNC Wake Event New Audio BIT_CLK WR 26H Data PR4 SDATA_OUT Slot 12 TAG TAG Slot 1 Slot 2 SDATA_IN Slot 12 TAG TAG Slot 1 Slot 2 Figure 40. AC-Link Wake Up Function by SDATAIN 3. SDATAIN Output SDATAIN pin goes to "H" when pen interrupt is enable, AC-link is powered-down and pen touch is detected. SDATAIN pin goes to "L" after SYNC signal is changed to "L" regardless of the pen touch detection. The AK4650 operates same as WARM RESET by receiving this SYNC signal. REV 0.6 - 53 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] 4. Wake Up Time The AK4650 can measures the touch screen position by 12bit ADC at arround 50ms from power-down state. (1) Wake Up from PR4 bit = "1" and PR5 bit = "1" The time from pen touch to position measurement available dependes on CPU, X'tal oscillator and the driver in addition to the AK4650. T5 and T7 depend on the AK4650. T7 is less than 1s. T5 (X'tal oscillation stable and BITCLK is output) is 20ms. T1 : From pen touch to SDATAIN output => depends on touch screen T2 : The AK4650 outputs SDATAIN and CPU outputs SYNC => depends on CPU T3 : SYNC "H" time => depends on CPU, more than 1s T4 : From SYNC falling edge to X'tal oscillation start => depends on CPU T5 : X'tal oscillation stable and BITCLK is output => depends on X'tal T6 : From CPU receives BITCLK to CPU outputs SYNC => depends on CPU T7 : From the AK4650 receives SYNC to the AK4650 outputs CODEC Ready => 162.8ns T8 : From CPU receives CODEC Ready to CPU reads ADC data => depends on CPU TSC T ouch IN T N S D A T A _ IN SYN C C r y s t a l O c ila t o r B IT C L K 1 2 b it A D C T2 T1 T3 T4 T5 T6 T7 T8 Figure 41. AC-Link Wake Up Timing (PR5 bit = "1") 5. Pen Interrupt The AK4650 outputs pen interrupt signal when pen interrupt is enabled and pen touch is detected. (1) When PENINT bit is "1", INTN pin goes to "L" (2) When AC-Link operates, GINT bit is "1" and SLOT bit is "1", bit 0 of slot 12 on SDATAIN goes to "1". (3) When PINTR bit is "1", DTPEN bit (Addr=6AH: D2) output the pen touch detection result. GPIO pin of the controller is not needed in case of (2) or (3). REV 0.6 - 54 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] 12bit ADC Data Reception Method 1. Selection of data reception method The AK4650 supports the following two method for 12bit ADC data reception which is selected by SLOT bit. SLOT bit 0 12bit ADC data reception method "Register" Default The AK4650 reports the measurement result (12bit ADC data) to the control register, then controller gets the data by reading the register of 74H, 76H and 78H. "Slot" The AK4650 reports the measurement result (12bit ADC data) to slot 5, slot 6 or slot 12, then controller gets the data from the asigned slot. Table 43. 12bit ADC data reception method 1 2. Measurement Mode Setting A2-0 and SER bits set the measurement mode (Table 44). PM12AD and PMVREF bits control the 12bit ADC power-up/down. DLY3-0 bits set the wait time from mode setting to measurement (Table 46). ADFLT bit sets the averaging of four data or not (Table 47). If these modes are changed during wait time, 12bit ADC is reset and starts with latest mode setting. A2-0, SER bit A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SER 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 XP OFF OFF OFF OFF OFF ON OFF OFF OFF OFF OFF ON OFF Driver switch status XN OFF OFF OFF ON ON ON OFF OFF OFF ON ON ON OFF YP OFF ON OFF ON ON OFF OFF OFF ON ON ON OFF OFF YN OFF ON OFF OFF OFF OFF OFF OFF ON OFF OFF OFF OFF ADC Input (AIN) AIN+ AIN- TEMP0 XP VBAT XP(Z1) YN(Z2) YP IN1 TEMP1 XP XP(Z1) YN(Z2) YP IN2 GND GND GND GND GND GND GND GND YN XN XN XN GND Reference voltage (VREF) VREF+ VREF- VREF VREF VREF VREF VREF VREF VREF VREF YP YP YP XP VREF GND GND GND GND GND GND GND GND YN XN XN XN GND Measurement item TEMP0 temperature (Default) Y-axis Battery voltage Pen pressure (Z1) Pen pressure (Z2) X-axis IN1 input TEMP1 temperature N/A Y-axis N/A Pen pressure (Z1) Pen pressure (Z2) X-axis IN2 input NA Table 44. 12bit ADC measurement mode REV 0.6 - 55 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] PM12AD 0 0 PMVREF x x PINTE 0 1 INTN Disable Enable VREF x x 1 1 x x 0 1 Disable Auto x x x x 0 1 x x x OFF x ON Table 45. 12bit ADC Power-up/down control (x: Don't care) Function 12bit ADC is powered down. Touch screen driver switch is open. The AK4650 waits for pen touch. 12bit ADC is powered down. Touch screen driver switch is open (though XP pin is TSVDD and YN pin is TSVSS). 12bit ADC is always powered up. After the measurement of XY or XYZ, 12bit ADC is automatically powered down and the AK4650 waits for pen touch. PMVREF bit controls the VREF power-up/down. DLY3-0 bit Wait time 0H 1TS Default 1H 2TS 2H 4TS 3H 8TS 4H 12TS 5H 16TS 6H 24TS 7H 32TS 8H 48TS 9H 64TS AH 96TS BH 128TS CH 160TS DH 192TS EH 224TS FH 256TS Table 46. Wait time from mode setting to measurement (1TS = 1SYNC period = 20.83s@fs=48kHz) ADFLT bit 0 Filter Data is not averaged. The AK4650 Default outputs one measurement result. 1 Four data are averaged. Table 47. 12bit ADC data filtering (SLOT bit = "0") REV 0.6 - 56 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] 3. Register Read The AK4650 supports the following three measurement methods which are selected by ADMODE1-0 bits. (1) 74H Register Read (2) XY Measurement Mode (3) XYZ Measurement Mode ADMODE 1-0 bits Measurement Method 00 74H Register Read 01 XY measurement mode 10 XYZ measurement mode 11 Reserved Table 48. 12bit ADC measurement mode setting 3-1. 74H Register Read Method The AK4650 reports the measurement result set by A2-0 and SER bits to the control register address 74H. The controller gets the measurement result by reading the control register address 74H. 74H register is cleared by PM12AD bit = "0". 74H consists of the followings: : 0: Measurement is not completed. 1: Measurement result is reported to D11-0. D14-12(A2-0) : Measurement mode (A2-0 bits) D11-0 : Measurement results (12bit) 3-1-1.ADFLT bit = "0" : No average (1) 70H(ADFLT, DLY3-0, ADEXE1-0) is set. A2-0 and SER bits set the measurement mode at the same time, and 12bit ADC is powered-up by setting PM12AD bit = "1". (2) After the wait time set by DLY3-0 bits, the measurement is available. (3) When 74H is read, then 12bit ADC is executed, data is reported to 74H, and the measurement mode is reported at next SYNC. D15(ADE) Default SYN C PM 12AD , P D 1 - 0 b its A 2 - 0 , S E R ,b it 101 001 1010 0010 R ead C om m and 74h 74h 74h S e n d A D C D a ta ADC M ode X M e a s u re Y M e a s u re 1 2 b it A D C DELAY W a it X -M e a s u re W a it X -M e a s u r e W a it DELAY W a it Y -M e a s u r e W a it P e n W a it A D E b it D 1 1 - D 0 b its XXX X -P o s X -P o s Y -P os DLY3-0 bits = "0H" Figure 42. X and Y position measurement sequence (ADFLT bit = "0") REV 0.6 - 57 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] 3-1-2.ADFLT bit = "1" : Averaging of four data (1) 70H (ADFLT, DLY3-0 and ADEXE1-0) is set. A2-0 and SER bits set the measurement mode at the same time, and 12bit ADC is powered-up by setting PM12AD bit = "1". (2) After the wait time set by DLY3-0 bits, the measurement is executed for four times and the averaged result is reported to 74H. (3) When 74H is read, the data of 74H is output. SYN C PM 12AD , P D 1 - 0 b its A 2 - 0 , S E R ,b it 101 1010 0010 R ead C om m and 74h 74h S e n d A D C D a ta ADC M ode X M e a s u re Y M e a s u re 1 2 b it A D C DELAY X -M e a s u re W a it DELAY Y -M e a s u r e W a it A D E b it D 1 1 - D 0 b its XXX X -P o s Y -P os DLY3-0 bits = "1H" Figure 43. X and Y position measurement sequence (ADFLT bit = "1") 3-2. X-Y Measurement Mode When ADMODE1-0 bits are set to "01" and PM12AD bit is "1", the AK4650 measures X-position at first, Y-position at second, and reports X-position to 74H, Y-position to 76H, respectively, regardless of A2-0 and SER bits. 74H and 76H registers are cleared by PM12AD bit = "0". (1) 70H(ADFLT, DLY3-0, MSR1-0, ADEXE1-0) is set. ADMODE1-0 bits should be set to "01" at the same time, and 12bit ADC is powered-up by setting PM12AD bit = "1". (2) After the wait time set by DLY3-0 bits, the AK4650 measures X-position and reports the result to 74H. When ADFLT bit is "1", averaged data of four measurement results is reported to 74H. (3) After X-position measurement and the wait time set by DLY3-0 bits, the AK4650 measures Y-position and reports the result to 76H. When ADFLT bit is "1", averaged data of four measurement results is reported to 76H. (4) After the measurement, ADMODE1-0 bits are automatically reset to "00". (5) When PINTE bit = "1", 12bit ADC is powered-down and the AK4650 waits for pen touch. SYN C PM 12AD , P D 1 - 0 b its A D M O D E 1 - 0 b its 100 01 ADC M ode X M e a s u re Y M e a s u re 1 2 b it A D C DELAY X M e a s u re DELAY y M e a s u re P E N -W a it 7 4 H :A D E b it 7 4 H :D 1 1 - D 0 b it s XXX X - P o s itio n 7 6 H :A D E b it 7 6 H :D 1 1 - D 0 b it s XXX Y - P o s itio n DLY3-0 bits = "2H" Figure 44. X and Y position measurement sequence When ADMODE1-0 bit is set to "01" again, then the AK4650 set ADE bit as "0" and measurement is executed again. REV 0.6 - 58 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] 3-3. XYZ Measurement Mode When ADMODE1-0 bits are set to "10" and PM12AD bit is "1", the AK4650 measures X-position at first, Y-position at second, the item set by A2-0 and SER bits at third, and reports X-position to 74H, Y-position to 76H, third result to 78H, respectively. 74H, 76H and 78H registers are cleared by PM12AD bit = "0". (1) 70H(ADFLT, DLY3-0, MSR1-0, ADEXE1-0) is set. Measurement mode should be set by A2-0 and SER bits, and ADMODE1-0 bits should be set to "10" at the same time. 12bit ADC is powered-up by setting PM12AD bit = "1". (2) After the wait time set by DLY3-0 bits, the AK4650 measures X-position and reports the result to 74H. When ADFLT bit is "1", averaged data of four measurement results is reported to 74H. (3) After X-position measurement and the wait time set by DLY3-0 bits, the AK4650 measures Y-position and reports the result to 76H. When ADFLT bit is "1", averaged data of four measurement results is reported to 76H. (4) After Y-position measurement and the wait time set by DLY3-0 bits, the AK4650 measures the item set by A2-0 and SER bits, and reports the result to 78H. When ADFLT bit is "1", averaged data of four measurement results is reported to 78H. (5) After the measurement, ADMODE1-0 bits are automatically reset to "00". (6) When PINTE bit = "1", 12bit ADC is powered-down and the AK4650 waits for pen touch. SYN C PM 12AD , PM VREF, P IN T E b its A D M O D E 1 - 0 b its 101 10 ADC M ode X M e a s u re Y M e a s u re Z 1 M e a s u re 1 2 b it A D C DELAY X M e a s u re DELAY y M e a s u re DELAY Z 1 M e a s u re P E N - W a it 7 4 H :A D E b it 7 4 H :D 1 1 - D 0 b it s XXX X - P o s itio n 7 6 H :A D E b it 7 6 H :D 1 1 - D 0 b it s XXX Y - P o s itio n 7 8 H :A D E b it 7 8 H :D 1 1 - D 0 b it s XXX Z 1 - P o s itio n DLY3-0 bits = "1H" Figure 45. X, Y and Z position measurement sequence (ADFLT bit = "1", A2-0 bits = "011", SER bit = "0") When ADMODE1-0 bit is set to "10" again, then the AK4650 set ADE bit as "1" and measurement is executed again. REV 0.6 - 59 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] 4. Method using SDATAIN Slot When SLOT bit is "1", 12bit ADC data is output via slot 5, 6 or 12 of SDATAIN. When SLOTNO1-0 bits are "00", "01" or "10", slot 5, 6 or 12 is used, respectively. Output data is 16bit. The measurement result is output only when 12bit ADC is executed. When data is output, tag bit for slot 5, 6 or 12 (bit 10, 9 or 3) is set to "1". When ADC is not executed, tag bit is set to "0" and data of slot 5, 6 or 12 are set to all "0". SLOTNO1-0 bits Slot number X Not used Default 00 Slot 5 01 Slot 6 1 10 Slot 12 11 Reserved Table 49. Slot number setting for 12bit ADC measurement result output : "1" when data is valid. ==> Tag bit in slot 0 is also set to "1" when data is output. Bit 18-16 : Measurement mode (A2-0 bit) Bit 15-4 : 12bit ADC data In this mode, ADFLT bit is ignored. Even if ADFLT bit is set to "1", four data average is not executed. The AK4650 supports the following three measurement modes: (1) Sequential measurement of set item (2) XY measurement mode (3) XYZ measurement mode ADMODE1-0 bits Measurement method 00 Sequential measurement of set item 01 XY measurement mode 10 XYZ measurement mode 11 Reserved Table 50. 12bit ADC measurement mode setting Bit 19 SLOT bit 0 Default 4-1. Sequential measurement of set item The AK4650 measures the item set by A2-0 and SER bits sequentially, and outputs the results via slot. When 12bit ADC is powered-down, bit 19 is "0". (1) When SLOT bit = "1", pen touch waiting state (PM12AD bit = "0") should set. (2) When the controller receives PEN Interrupt, the controller should set PM12AD bit = "1". Then data is output via slot. (3) If 12bit ADC is powered-up by setting PM12AD bit = "1" and measurement item is set by A2-0 and SER bits, then the set item is sequentially measured after the wait time set by DLY3-0 bits. If the measurement is not completed in one SYNC period, bit 19 (ADE) is "0". REV 0.6 - 60 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] 4-2. X-Y Measurement Mode When PM12AD bit is "1" and then ADMODE1-0 bits are set to "01", the AK4650 measures X-position for times set by MSR1-0 bits at first, Y-position for times set by MSR1-0 bits at second, regardless of A2-0 and SER bits. Measurement results are output via slot after wait time set by DLY3-0 bits. (1) (2) (3) (4) When SLOT bit = "1", pen touch waiting state (PM12AD bit = "0" and PINTE bit = "1") should be set. When the controller receives PEN Interrupt, the controller should set PM12AD bit = "1". Then data is output via slot. 12bit ADC is powered-up by setting PM12AD bit = "1". ADMODE1-0 bits should be set to "01" at the same time. After the wait time set by DLY3-0 bits, the AK4650 measures X-position for times set by MSR1-0 bits and outputs the result via slot. (5) After X-position measurement and the wait time set by DLY3-0 bits, the AK4650 measures Y-position for times set by MSR1-0 bits and outputs the result via slot. (6) After Y-position measurement, 12bit ADC is powered-down and the AK4650 waits for pen touch. SYN C S lo t b it P M 1 2 A D ,P D 1 - 0 b its A D M O D E 1 - 0 b its 000 100 00 01 ADC M ode X M e a s u re Y M e a s u re 1 2 b it A D C P E N -W a it DELAY X M e a s u re X M e a s u re X M e a s u re X M e a s u re DELAY y M e a s u re y M e a s u re y M e a s u re y M e a s u re P E N -W a it S lo t B IT 1 9 S lo t B I T 1 8 - 1 6 000 101 000 001 000 S lo t B IT 1 5 - 4 0 X pos X Pos X pos X pos 0 y pos y pos y pos y pos 0 DLY3-0 bits = "1H", MSR1-0 bits = "0H" Figure 46. X and Y position measurement sequence MSR1-0 bit Measurement times 00 4 times Default 01 8 times 10 16 times 11 32 times Table 51. Measurement times (SLOT bit = "1") REV 0.6 - 61 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] 4-3. X-Y-Z Measurement Mode When PM12AD bit is "1" and then ADMODE1-0 bits are set to "10", the AK4650 measures X-position for times set by MSR1-0 bits at first, Y-position for times set by MSR1-0 bits at second, the item set by A2-0 and SER bits for times set by MSR1-0 bits at third. Measurement results are output via slot after wait time set by DLY3-0 bits. (1) (2) (3) (4) When SLOT bit = "1", pen touch waiting state (PM12AD bit = "1" and PINTE bit = "1") should be set. When the controller receives PEN Interrupt, the controller should set SLOT bit = "1". Then data is output via slot. 12bit ADC is powered-up by setting PM12AD bit = "1". ADMODE1-0 bits should be set to "10" at the same time. After the wait time set by DLY3-0 bits, the AK4650 measures X-position for times set by MSR1-0 bits and outputs the result via slot. (5) After X-position measurement and the wait time set by DLY3-0 bits, the AK4650 measures Y-position for times set by MSR1-0 bits and outputs the result via slot. (6) After Y-position measurement and the wait time set by DLY3-0 bits, the AK4650 measures the item set by A2-0 and SER bits for times set by MSR1-0 bits and outputs the result via slot. (7) After the measurement, 12bit ADC is powered-down and the AK4650 waits for pen touch. 5. ADEXE pin When the AK4650 measures the position during the data is sent to LCD, the position measurement result may have some error caused by the noise from LCD. The AK4650 prepares the measurement mode by using sync signal from LCD after data transferring is completed. The sync signal is input to ADEXE pin of the AK4650. ADEXE1-0 bit 00 01 10 11 Measurement mode ADC is executed regardless of ADEXE pin. ADC is executed at ADEXE pin = "". ADC is executed at ADEXE pin = "". Reserved Table 52. ADEXE mode Default Method using Slot 12 of SDATAIN When SLOT bit is "1", pen interrupt and headphone jack detection results are output via slot 12 of SDATAIN. Bit 1: Headphone jack detection result Bit 0: Pen interrupt REV 0.6 - 62 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Connection with Digital AC '97 Controller The AK4650 communicates with its companion AC `97 controller via a digital serial link, "AC-link". All digital audio streams, and command/status information are communicated over this point to point serial interconnect. A breakout of the signals connecting the two is shown in the following figure. AC'97 Controller SYNC BITCLK SDATAOUT SDATAIN RESET# AK4650 Figure 47. Connection between AK4650 and AC '97 controller RESETN BITCLK SYNC SDATAIN SDATAOUT (Input) (Output) (Input) (Output) (Input) : Control signal to reset the AK4650 : 12.288MHz clock output from the AK4650 : Control signal to synchronize the AK4650 with AC'97 controller : Data signal input to the controller (output from the AK4650) : Data signal output to the controller (input from the AK4650) Digital Interface The AK4650 incorporates a 5 pin digital serial interface that links it to the AC '97 controller. AC-link is a bi-directional, fixed rate(48kHz), serial PCM digital stream. It handles input/output audio streams and 12bit ADC results, as well as control register accesses employing a time division multiplexed (TDM) scheme. The AC-link architecture divides each audio frame into 12 outgoing and 12 incoming data streams, each with 20-bit sample resolution. DAC and ADC resolution of the AK4650 is 16 bit resolution. The data streams currently defined by the AC `97 specification include: PCM Playback 2 output slots 2 channel composite PCM output stream PCM Record data 2 input slots 1 channel composite PCM input stream Control 2 output slots Control register write port Status 2 input slots Control register read port 12bit ADC data 3 input slots 12bit ADC data input stream SYNC, fixed at 48kHz, is derived by dividing down the serial bit clock (BITCLK) output from the AK4650. BITCLK, fixed at 12.288 MHz, provides the necessary clocking granularity to support 12, 20-bit outgoing and incoming time slots. AC-link serial data is transitioned on each rising edge of BITCLK. The receiver of AC-link data, the AK4650 for outgoing data and AC '97 controller for incoming data, samples each serial bit on the falling edges of BITCLK. The AC-link protocol provides for a special 16-bit slot (Slot 0) wherein each bit conveys a valid tag for its corresponding time slot within the current audio frame. A "1" in a given bit position of slot 0 indicates that the corresponding time slot within the current audio frame has been assigned to a data stream, and contains valid data. If a slot is "Tagged" invalid, it is the responsibility of the source of the data (the AK4650 for the input stream, AC '97 controller for the output stream), to stuff all bit positions with 0's during that slot's active time. REV 0.6 - 63 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] SYNC remains high for a total duration of 16 BITCLKs at the beginning of each audio frame. The portion of the audio frame where SYNC is high is defined as the "Tag Phase". The remainder of the audio frame where SYNC is low is defined as the "Data Phase". Note that SDATAOUT and SDATAIN data is delayed one BITCLK because AC'97 controller causes SYNC signal high at a rising edge of BITCLK which initiates a frame. "Output" stream means the direction from AC'97 controller to the AK4650, and "Input" stream means the direction from the AK4650 to AC'97 controller. AC-Link Protocol Slot SYNC 0 1 2 3 4 5 6 7 8 9 10 11 12 SDATA OUT TAG Command Command PCM(dac) PCM(dac) Address Data Left Right All "0" All "0" All "0" All "0" All "0" All "0" All "0" All "0" SDATA IN TAG Status Address Status Data PCM(adc) Left All "0" 12bit ADC 12bit ADC Data Data All "0" All "0" All "0" All "0" All "0" 12bit ADC Data Tag Phase Data Phase 48kHz Figure 48. AC-Link protocol AC-link protocol identifies 13 slots of data per frame. The frequency of SYNC is fixed to 48kHz. Only Slot 0, which is the Tag phase, is 16bits, all other slots are 20bits in length. These slots are explained in later sections. REV 0.6 - 64 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] 1) AC-Link Audio Output Frame (SDATAOUT) [Slot 0] SYNC BIT_CLK SDATA_IN Valid Frame Slot1 Slot2 Slot3 Slot4 Slot5 Slot6 Slot7 Slot8 Slot9 Slot10 Slot11 Slot12 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 "1/0" "1/0" "1/0" "1/0" "1/0" "0" "0" Bit8 "0" Bit7 "0" Bit6 "0" Bit5 "0" Bit4 "0" Bit3 "0" Bit2 "0" Bit1 "0" Bit0 "0" 1 BIT_CLK delay Slot 0 Slot 1 Figure 49. Slot 0 Slot 0 consists of sixteen bits (bit 15-0). Bit 15-11 are available in the AK4650. Each bit means valid by "1" and invalid by "0". Bit 15 (Valid Frame bit): Validity of the frame "1" = At least one of bit 14-11 (slot 1-4) must be valid. Bit 10-0 are ignored. "0" = The AK4650 ignores all following information in the frame. Bit 14 (Slot 1 valid bit): Validity of slot 1 (command address input) Bit 13 (Slot 2 valid bit): Validity of slot 2 (command data input) Bit 12 (Slot 3 valid bit): Validity of slot 3 (DAC Left data input) Bit 11 (Slot 4 valid bit): Validity of slot 4 (DAC Right data input) If each bit is "0", the AK4650 ignores the slot indicated by "0". On the other hand, if each bit is "1", the slot is valid. Bit 10-0 should be "0". A new audio output frame begins with a low to high transition of SYNC. SYNC is synchronous to the rising edge of BITCLK. On the immediately following falling edge of BITCLK, the AK4650 samples the assertion of SYNC. This falling edge marks the time when both sides of AC-link are aware of the start of a new audio frame. On the next rising of BITCLK, the AC '97 controller transitions SDATAOUT into the first bit position of slot 0 (Valid Frame bit). Each new bit position is presented to AC-link on a rising edge of BITCLK, and subsequently sampled by the AK4650 on the following falling edge of BITCLK. This sequence ensures that data transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned. Data should be sent to the AK4650 with MSB first through the SDATAOUT. REV 0.6 - 65 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Table 53 shows the relationship of bit 14&13 and the Read/Write operation. Bit 15 Valid Frame 1 1 1 1 Bit 14: Slot1 Valid Bit (Command Address) 1 0 1 Bit 13: Slot 2 Valid Bit (Command Data) 1 1 0 Read/Write Operation Read/Write (Normal Operation) Ignore Read: Normal Operation Write: Ignore Ignore 0 0 Table 53. AK4650 Addressing: Slot 0 Tag Bits [Slot 1]: Command Address Port Slot1 gives the address of the command data, which is given in the slot 2. The AK4650 has 30 valid registers of 16bit data. See "Mixer Registers". BIT_CLK SDATA_OUT Bit19 Bit18 Bit17 Bit16 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit2 Bit1 Bit0 Bit19 Bit18 Bit17 Bit16 "1/0" "1/0" "1/0" "1/0" "1/0" "1/0" "1/0" "1/0" "0" "0" "0" "0" "0" "0" Slot 0 Slot 1 Command Address Port Slot 2 Figure 50. Slot 1 Bit 19: Bit 18-12: Bit 11-0: Read/Write command (1bit; "1"=read, "0"=write) Control Register Index (7bit; see "Mixer Registers" for the detail) Reserved (12bit; "0") Bit 18 of this slot 1 is equivalent to the most significant bit of the index register address. The AK4650 ignores bit 11-0. These bits will be reserved for future enhancement and must be staffed with 0's by the AC'97 controller. [Slot 2]: Command Data Port BIT_CLK SDATA_OUT Bit19 Bit18 Bit17 Bit16 Bit15 Bit14 Bit13 Bit12 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit19 Bit18 Bit17 Bit16 "1/0" "1/0" "1/0" "1/0" "1/0" "1/0" "1/0" "1/0" "1/0" "1/0" "0" "0" "0" "0" Slot 1 Slot 2 Command Data Port Slot 3 Figure 51. Slot 2 Bit19-4: Bit3-0: Control Register Write Data (16bit) (If bit 19 of slot 1 is "1", all bit19-4 should be "0".) Reserved (4bit; "0") If bit 19 in slot 1 is "0", the AC'97 controller must output Command Data Port data in slot 2 of the same frame. If the bit 19 in slot 1 is "1", the AK4650 will ignore any Command Data Port data in slot 2. Bit19 of this slot 2 is equivalent to D15 bit of mixer register value. REV 0.6 - 66 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] [Slot 3]: PCM Playback Left Channel (16bit) The AK4650 uses the playback (DAC) data format in slot 3 for left channel. Playback data format is MSB first. Data format is 16bits 2's complement. AC'97 controller should stuff bit 3-0 with "0". If valid bit (slot 3) in the slot 0 is invalid ("0"), the AK4650 interprets the data as all "0". Bit 19-4: Playback data (16bit) Bit 3-0: "0" (4bit) [Slot 4]: PCM Playback Right Channel (16bit) The AK4650 uses the playback (DAC) data format in slot 4 for right channel. Playback data format is MSB first. Data format is 16bits 2's complement. AC'97 controller should stuff bit 3-0 with "0". If valid bit (slot 4) in the slot 0 is invalid ("0"), the AK4650 interprets the data as all "0". Bit 19-4: Playback data (16bit) Bit 3-0: "0" (4bit) [Slot 5-12]: Not implemented in the AK4650 REV 0.6 - 67 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] 2) AC-Link Input Frame (SDATAIN) Each AC-link frame consists of one 16bit tag phase and twelve 20bit slots used for data and control. [Slot 0] Slot 0 is a special time frame, and consists of 16bits. Slot 0 is also named the Tag phase. The AK4650 supports bits 15-9 and bit 3. Each bit indicates "1"=valid(normal operation) or ready, "0"=invalid (abnormal operation) or not ready. If the first bit in the slot 0 (Bit15 = "Codec Ready") is valid, the AK4650 is ready for normal operation. If the "Codec Ready" bit is invalid, the following bits and remaining slots are all "0". AC'97 controller should ignore the following bits in the slot 0 and all other slots. When the ADC sampling rate is set for less than 48kHz, then bits 12 and 11 in slot 0 (corresponds to slot 3 and slot 4 respectively) will be 1's when valid data is transferred in SDATAIN, and will be 0's when no data is transmitted. < "On-demand" base data transaction> For variable sample rate input, the tag bit for each input slot indicates whether valid data is present or not. Thus, even in variable sample rate mode, the AK4650 is always the master. For SDATAIN (AK4650 to Controller), the AK4650 sets the TAG bit. For SDATAOUT (Controller to AK4650), the AK4650 sets the SLOTREQ bit and then checks for the TAG bit in the next frame. AK4650 expects Controller will reply TAG bit in the next frame correctly. Bit 14 means that Slot 1 (Status Address) output is valid or invalid. And Bit 13 means that Slot 2 (Status Data) is valid or invalid. Table 54 shows the relationship between bit 14,13 and each Status of the AK4650. Bit 15 (Codec Ready) 1 Bit 14 (Status Address) 1 Bit 13 (Status Data) 1 Status 1 1 1 1 0 0 0 1 0 There is a Read Command in the previous frame. Then both Slot 1 and Slot 2 output normal data. If the access to non-implemented register or odd register is requested, the AK4650 returns "valid" 7-bit register address in slot 1 and returns "valid" 0000h data in slot 2 on the next AC-link frame. Prohibited or non-existing Prohibited or non-existing There is no Read Command in the previous frame. Bits 19-12 and 9-0 in Slot 1 are set to "0". And Slot 2 outputs all "0". Table 54. SDATAIN Slot0 Note 37. The above Read sequence is done as response for previous frames read command. That is, if the previous frame is the Write Command, AK4650 outputs bit14 ="0", bit13 ="0" and slot 1&2 = All"0", if there is no SLOTREQ. Note 38. The Bits 14 and 13 in Slot 0 is independent of the SLOTREQ Bits 11 and 10 in Slot 1 which the AK4650 supports. Bit12 means the output of Slot 3 (PCM(ADC) Left) is valid or invalid. Bit 11 is same as bit 12. Slot 4 is all "0" regardless of bit 11. When ADEXE1-0 bits are not "00" and SLOT bit is "1", Tag bit corresponding to the slot set by SLOTNO1-0 bits (Slot 5=Bit 10, Slot 6=Bit 9, Slot 12=Bit 3) are fixed to "1" (valid). Bits 8-4 and 2-0 are occupied with "0". REV 0.6 - 68 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] A new audio input frame begins with a low to high transition of SYNC. SYNC is synchronous to the rising edge of BITCLK. On the immediately following falling edge of BITCLK, the AK4650 samples the assertion of SYNC. This falling edge marks the time when both sides of AC-link are aware of the start of a new audio frame. On the next rising of BITCLK, the AK4650 transitions SDATAIN into the first bit position of slot 0 ("Codec Ready" bit). Each new bit position is presented to AC-link on a rising edge of BITCLK, and subsequently sampled by the AC '97 controller on the following falling edge of BITCLK. This sequence ensures that data transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned. SYNC BIT_CLK SDATA_IN Codec Ready Slot1 Slot2 Slot3 Slot4 Slot5 Slot6 Slot7 Slot8 Slot11 Slot12 "1/0" "1/0" "1/0" "1/0" "1/0" "1/0" "1/0" "0" Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 "0" Bit7 "0" Bit4 "1/0" "0" Bit3 Bit2 "0" Bit1 "0" Bit0 Slot 0 Slot 1 Figure 52. Slot 0 [Slot 1]: Status Address Port Audio input frame slot 1's stream echoes the control register index, for historical reference, for the data to be returned in slot 2. (Assuming that slot 1 valid bit and slot 2 valid bit in the slot 0 had been tagged "valid" by the AK4650.) BIT_CLK SDATA_IN Bit19 Bit18 Bit17 Bit16 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit19 "0" "1/0" "1/0" "1/0" "1/0" "1/0" "1/0" "1/0" "1/0" "1/0" "0" "0" "0" "0" "0" "0" "0" "0" "0" "0" Slot 0 Slot 1 Status Address Port Slot 2 Figure 53. Slot 1 This address shows register index for which data is being returned in the slot 2. This address port is the copy of slot 1 of the output frame, and index address input to SDATAOUT is looped back to the AC'97 controller through SDATAIN even for non-supported register. For "On Demand" base data transaction, when the DAC sampling rate is set less than 48kHz, then AK4650 will request new audio data as required by setting the SLOTREQ bits 11 and 10 in slot 1 to 0's. When no data is required to support the selected sampling rate, these bits will be 1's. When SLOTREQ bits are asserted as "send data request" during the current frame on SDATAIN, AC'97 digital controller should send data onto the corresponding slot in the next frame on SDATAOUT. If VRA bit is set to "0", SLOTREQ bits always show "0" and sample rate is forced to 48kHz. SLOTREQ Bit 19 18-12 11 10 9-0 Description Reserved (Set to "0") Control Register Index (7bit; Set to "0" if tagged invalid) Slot 3 Request: PCM Lch "0": send data request, "1": do not send Slot 4 Request: PCM Rch "0": send data request, "1": do not send Reserved (10bit; Set to "0") Table 55. SLOTREQ bit REV 0.6 - 69 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] [Slot 2]: Status Data Port Status data addressed by command address port of Output Stream is output through SDATAIN pin. Bit 19-4 Control Register Read Data (16bit; the contents of indexed address in the slot 1) Bit 3-0 "0" (4bit) Note that the address of Status Data Port data are consistent with Status Address Port data of the slot 1 in the same frame. If the read operation is issued in the frame N by AC'97 controller, Status Data Port data is output through SDATAIN in the frame N+1. Note that data is output in only this frame, only one time and that the following frames are invalid if the next read operation is not issued. [Slot 3]: PCM Record Left Channel Record (ADC) data format is MSB first. Data format is 2's complement. As the resolution of the AK4650 is 16bit, lower 4 bits are ignored. If ADC block is powered down, slot 3 valid bit in the slot 0 is invalid ("0"), and data is output as all "0". Bit 19-4: Audio ADC left channel output (16bit) Bit 3-0: "0" (4bit) [Slot 4]: Reserved for future enhancement Bit 19-0 "0" [Slot 5]: 12bit ADC data for TSC When SLOT bit = "1" and SLOTNO1-0 bits = "00", 12bit ADC data is output. Bit 19: ADE (1bit; "0"=Invalid, "1"=Valid) Bit 18-16: A2-0 (3bit; Measurement mode) Bit 15-4: D11-0 (12bit; 12bit ADC data) Bit 3-0: "0" (4bit) [Slot 6]: 12bit ADC data for TSC When SLOT bit = "1" and SLOTNO1-0 bits = "00", 12bit ADC data is output. Bit 19: ADE (1bit; "0"=Invalid, "1"=Valid) Bit 18-16: A2-0 (3bit; Measurement mode) Bit 15-4: D11-0 (12bit; 12bit ADC data) Bit 3-0: "0" (4bit) [Slot 7-11]: Reserved for future enhancement Bit 19-0 "0" [Slot 12]: 12bit ADC data for TSC, pen touch and headphone jack detection results When SLOT bit = "1" and SLOTNO1-0 bits = "00", 12bit ADC data is output. When SLOT bit = "1", pen touch and headphone jack detection results are output regardless of SLOTNO1-0 bits. Bit 19: ADE (1bit; "0"=Invalid, "1"=Valid) Bit 18-16: A2-0 (3bit; Measurement mode) Bit 15-4: D11-0 (12bit; 12bit ADC data) Bit 3-2: "0" (2bit) Bit 1: DTHPJ (1bit; "0"=Not inserted, "1"=Inserted) Bit 0: DTPEN (1bit; "0"=Not touched, "1"=Touched) REV 0.6 - 70 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Power On Note that AK4650 must be in cold reset at power on and RESETN must be "L" until master crystal clock becomes stable, or cold reset must be done once after master clock is stable. Vdd RESET# SDATA_OUT="L" SYNC="L" BIT_CLK Initialize Registers start up crystal oscillation Trst2clk Figure 54. Power On Timing Cold Reset Note that both SDATAOUT and SYNC must be "L" at the rising edge of RESETN for cold reset. The AK4650 initializes all registers including the Power-down Control Registers, BIT-CLK is reactivated and each analog output except for HP-Amp is in Hi-Z state while RESETN pin is "L". At the rising edge of RESETN, the AK4650 starts the initialization of ADC and DAC, which takes 1028TS cycles. After that, the AK4650 is ready for normal operation. At that time, VRA bit is its default value ("0"). Therefore, fs=48kHz and TS=1/fs=20.83s. Status bit in the slot 0 is "0" (not ready) when the AK4650 is in RESET period ("L") or in initialization process. After initialization cycles, the status bit goes to "1" (ready). Trst_low RESET# VIL SDATA_OUT= "L" SYNC= "L" BIT_CLK Trst2clk Figure 55. Cold Reset Timing REV 0.6 - 71 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Warm Reset The AK4650 initiates warm reset process by receiving a single pulse on the SYNC. The AK4650 clears PR4 bit and PR5 bit in the Power-down Control Register. However, warm reset does not influence PR0-3, 6 and 7 bits in Power-down Control Register. Note 39. SYNC signal should synchronize with BITCLK after AK4650 starts to output BITCLK clock. Note 40. If an external clock is used, external clocks should be supplied before issuing a sync pulse for warm reset. ADC and DAC require 1028TS for the initialization. Tsync_high SYNC Tsync2clk VIH BIT_CLK Figure 56. Warm Reset Timing Active Test Mode RESET# VIH SDATA_OUT Tsetup2rst SDATA_IN BIT_CLK HI-Z VIH Toff Figure 57. Activate Test Mode Timing Note 41. All AC-link signals are normally low through the trailing edge of RESETN. Bringing RESETN high for the rising edge of SDATAOUT causes the AK4650 AC-link outputs to go high impedance which is suitable for ATE in circuit testing. Note that the AK4650 enters in the ATE test mode regardless SYNC is high or low. Note 42. Once test modes have been entered, the only way to return to the normal operating state is to issue "cold reset" which issues RESETN with both SYNC and SDATAOUT "L". REV 0.6 - 72 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Register Map Reg Num 00H 02H 04H 06H 08H 0AH 0CH 0EH 10H 18H 1AH 20H 26H 28H 2AH 2CH 32H 60H 62H 64H 66H 68H 6AH 70H 72H 74H 76H 78H 7CH 7EH Name Reset Speaker Output Headphone Output Mono Output Boost Control PC_BEEP Volume Phone Volume Mic Volume Line In Volume PCM Out Volume Record Select General Purpose Powerdown Ctrl/Stat Extended Audio ID Ext'd audio Stat/Ctrl PCM Front DAC Rate PCM LR ADC Rate Power Management Signal Select ALC/DAC Control ALC Mode Control Volume Cotrol Detect Result 12bit ADC Control 1 12bit ADC Control 2 ADC Data 1 ADC Data 2 ADC Data 3 D15 0 SPPS HPMT MOMT X BPMT AUXMT MICMT LNMT SMUTE X X X 0 X SR15 SR15 MPWRE HPM X X X X PM12AD 1 ADE ADE ADE D14 0 X X X X X X X X ATTL6 X X PR6 0 X SR14 SR14 MPWRI X HPINT ALC2 X X ADFLT GINT A2 A2 A2 D13 0 X X X X X X X X ATTL5 X X PR5 X X SR13 SR13 X X REF5 ALC1 X X MSR1 PENINT A1 A1 A1 D12 0 X X X X X X X GL4 ATTL4 X X PR4 X X SR12 SR12 X X REF4 ZELMN X X MSR0 PINTR A0 A0 A0 D11 0 X X X BST1 X X X GL3 ATTL3 X X PR3 0 X SR11 SR11 X INBP REF3 LMAT1 X X DLY3 PMVRE F D11 D11 D11 D10 0 X X X BST0 X X X GL2 ATTL2 X X PR2 0 X SR10 SR10 X RNMD REF2 LMAT0 X X DLY2 PINTE D10 D10 D10 D9 0 X X X X X X X GL1 ATTL1 MICAD MDIF PR1 0 X SR9 SR9 X LNMP REF1 RGAIN X X DLY1 X D9 D9 D9 D8 0 X X X X X X X GL0 ATTL0 AUXAD MSEL PR0 0 X SR8 SR8 MCKPD DAHS REF0 LMTH X X DLY0 X D8 D8 D8 D7 0 X X X X X X X X X X LOOP X 0 X SR7 SR7 PMSPK AUXL DATTC X X X ADEXE 1 X D7 D7 D7 D6 0 X X X X X X MGAIN X ATTR6 X X X 0 X SR6 SR6 PMHPR MICL ATPU ROTM X X ADEXE 0 X D6 D6 D6 D5 1 X X X X X X IPGA5 X ATTR5 X X X 0 X SR5 SR5 PMHPL MICM ATSW ZTM1 X X ADMO DE1 X D5 D5 D5 D4 1 X X X X X GN4 IPGA4 GR4 ATTR4 X X X 0 X SR4 SR4 PMBPM DAMO HPDT ZTM0 ATS X ADMO DE0 X D4 D4 D4 D3 0 X X X X X GN3 IPGA3 GR3 ATTR3 X X 0 0 X SR3 SR3 PMLIN BPMHP TM1 WTM1 ATTM X A2 X D3 D3 D3 D2 0 X X MOGN2 X X GN2 IPGA2 GR2 ATTR2 X X ANL 0 X SR2 SR2 PMMO BPMSP TM0 WTM0 ATTS2 DTPEN A1 SLOTN O1 D2 D2 D2 D1 0 X X MOGN1 X X GN1 IPGA1 GR1 ATTR1 X X DAC 0 X SR1 SR1 PMAUX ALCS DEM1 LTM1 ATTS1 DTHPJ A0 SLOTN O0 D1 D1 D1 D0 0 X X MOGN0 X X GN0 IPGA0 GR0 ATTR0 X X ADC 1 VRA SR0 SR0 PMMIC MO2 DEM0 LTM0 ATTS0 DTMIC SER SLOT D0 D0 D0 Default 0030H 8000H 8000H 8000H 0000H 8000H 8008H 8008H 8808H 8000H 0200H 0000H 030CH 0001H 0000H BB80H BB80H 0000H 0103H 2D21H 0000H 0002H X 0001H 9400H x x x 414BH 4D10H Vendor ID1 Vendor ID2 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 Table 56. Register Map REV 0.6 - 73 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Speaker Output (02H) SPPS: Speaker-amp Power-Save-Mode (Table 38) 0: Normal Operation 1: Power Save Mode (Default) When the SPPS bit = "1", the Speaker-amp is in power-save-mode and the SPP pin becomes Hi-Z and SPN pin is set to HVDD/2 voltage. When the PMSPK bit = "1", this bit is valid. After the RESETN pin changes from "L" to "H", the PMSPK bit is "0", which powers down Speaker-amp Headphone Output (04H) HPMT: Headphone Amp Mute Control (Figure 26) 0: Mute OFF 1: Mute ON (Default) Mono Output (06H) MOMT: Mono Output Mute Control (Table 30) 0: Mute OFF 1: Mute ON (Default) MOGN2-0: MOUT Volume Control (Table 31) Default: "000" (+6dB) Boost Control (08H) BST1-0: Bass Boost Control (Table 24) Default: "00" (OFF) BEEP Volume (0AH) BPMT: BEEP Input Mute Control 0: Mute OFF 1: Mute ON (Default) Phone Volume (0CH) AUXMT: AUX Input Mute Control (Table 28) 0: Mute OFF 1: Mute ON (Default) GN4-0: AUX Input Volume Control (Table 28) Default: "08H" (0dB) MIC Volume (0EH) MICMT: Mic Input Mute Control (Table 14) 0: Mute OFF 1: Mute ON (Default) MGAIN: MIC-Amp Gain Control (Table 10) 0: 0dB (Default) 1: +20dB IPGA5-0: IPGA Control (Table 14) Default: "08H" (0dB) REV 0.6 - 74 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Line In Volume (10H) LNMT: Line Input Mute Control (Table 29) 0: Mute OFF 1: Mute ON (Default) GL4-0: Lch Line Input Volume Control (Table 29) Default: "08H" (0dB) GR4-0: Rch Line Input Volume Control (Table 29) Default: "08H" (0dB) PCM Volume (18H) SMUTE: Soft Mute Control (Figure 21) 0: Normal Operation (Default) 1: DAC outputs soft-muted Soft mute operation is independent of digital attenuator and is performed in the digital domain. ATTL/R6-0: Digital ATT Control (Table 25) Default: "00H"(0dB) Record Select Control Register (1AH) AUXAD: AUXIN to ADC enable 0: OFF (Default) 1: ON MICAD: IPGA to ADC enable 0: OFF 1: ON (Default) General Purpose (20H) LOOP: Internal Digital Loopback 0: OFF (Default) 1: ON When LOOP bit is "1", VRA bit should be "0". MSEL: Internal/External MIC Select (Table 9 at MDIF bit = "0") 0: Internal MIC (Default) 1: External MIC MDIF: Differential MIC Input Select (Table 9) 0: Single-ended Input (Default) 1: Differential Input REV 0.6 - 75 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Power Management (26H) PR6-0: Power Management (Table 6) Default: "0000011" (ADC, DAC Power down) REF: Internal VREF Power-up (Read only) 0: NOT Ready 1: Ready ANL: Analog Mixer Power-up (Read only) 0: NOT Ready 1: Ready DAC: DAC ready to accept data (Read only) 0: NOT Ready 1: Ready ADC: ADC ready to transmit data (Read only) 0: NOT Ready 1: Ready Extended Audio Status & Control (2AH) VRA: Enables Variable Rate Audio mode in conjunction with Audio Sample Rate Control Registers and tag-bit/SLOTREQ signaling. 0: OFF(Default). PLL is powered-down. 1: ON Audio Sample Rate control Registers (2CH, 32H) SR15-0: Sample Rate Control for DAC (2CH) and ADC (32H) (Table 4, Table 5) Default: "BB80H"(48kHz) These Sample Rate setting is done at VRA bit = "1". REV 0.6 - 76 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Power Management (60H) PMMIC: MIC Block (MIC-Amp and ALC1) Power Management 0: Power down (Default) 1: Power up PMAUX: AUX Input Power Management 0: Power down (Default) 1: Power up PMMO: Mono Line Output Power Management 0: Power down (Default) 1: Power up PMLIN: Stereo Line Input Power Management 0: Power down (Default) 1: Power up PMBPM: Mono Beep Input Power Management 0: Power down (Default) 1: Power up Even if PMBPM= "0", the path is still connected between BEEP pin and HP/SPK-Amp. BPMHP and BPMSP bits should be set to "0" to disconnect these paths, respectively. PMHPR: Headphone-Amp Rch Power Management 0: Power down (Default) 1: Power up PMHPL: Headphone-Amp Lch Power Management 0: Power down (Default) 1: Power up PMSPK: Speaker-Amp Power Management 0: Power down (Default) 1: Power up MCKPD: XTI pin pull down control 0: Master Clock input enable (Default) 1: XTI pin is internally pulled-down MPWRI: Internal MIC Power Supply Control (Table 11) 0: OFF (Default) 1: MIC Power is ON for Internal MIC. MPWRI bit is enabled when PMMIC bit = "1". MPWRE: External MIC Power Supply Control (Table 12) 0: OFF (Default) 1: MIC Power is ON for External MIC. MPWRE bit is enabled when PMMIC bit = "1". REV 0.6 - 77 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Signal Select (62H) MO2: Mono Output (MOUT2 pin) Enable 0: OFF 1: ON (Default) When MO2 bit = "0", MOUT2 pin outputs VCOM voltage. MOUT2 pin outputs signal when MO2 bit = "1" and PMSPK bit = "1". MOUT2 pin goes to Hi-Z state when PMSPK bit = "0". ALCS: ALC2 to Speaker-Amp Enable 0: OFF 1: ON (Default) BPMSP: BEEP to Speaker-Amp Enable 0: OFF (Default) 1: ON BPMHP: BEEP to Headphone-Amp Enable 0: OFF (Default) 1: ON DAMO: DAC to Mono Line Output Enable 0: OFF (Default) 1: ON MICM: IPGA to Mono Line Output Enable 0: OFF (Default) 1: ON MICL: IPGA to Headphone/Speaker-Amp Enable 0: OFF (Default) 1: ON AUXL: AUXIN to Headphone/Speaker-Amp Enable 0: OFF (Default) 1: ON DAHS: DAC to Headphone/Speaker-Amp Enable 0: OFF 1: ON (Default) LNMP: LIN/MPE pin Selection 0: MPE pin (Default) 1: LIN pin RNMD: RIN/MDT pin Selection 0: MDT pin (Default) 1: RIN pin INBP: IN2/BEEP pin Selection 0: BEEP pin (Default) 1: IN2 pin HPM: Mono Output Select of Headphone 0: Stereo (Default) 1: Mono [(L+R)/2] REV 0.6 - 78 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] ALC/DAC Control (64H) DEM1-0: De-emphases response (Table 23) Default: "01" (OFF) TM1-0: Soft Mute Time Select (Table 27) Default: "00" (1024/fs) HPDT: Headphone Jack Insertion Detection Function Enable 0: OFF (Default) 1: ON ATSW: Headphone/Speaker Automatic Switch Function Enable by Headphone Jack Insertion (Table 35, Table 36) 0: OFF 1: ON (Default) ATPU: Headphone-Amp Automatic Power-up Function Enable by Pen Touch (Figure 39) 0: OFF (Default) 1: ON DATTC: DAC Digital Attenuator Control Mode Select 0: Independent 1: Dependent (Default) When DATTC= "1", ATTL6-0 bits control both Lch and Rch at the same time. ATTR6-0 bits are not changed when the ATTL6-0 bits are written. REF5-0: Maximum IPGA value at ALC1 Recovery Operation (Table 21) Default: "2DH" (+19dB) During the ALC1 recovery operation, if the IPGA value exceeds the setting maximum value (REF5-0 bits) by gain operation, then the IPGA does not become larger than the maximum value. HPINT: INTN pin Output Enable for Headphone Jack Detection Default: "0" (OFF) When HPINT bit = "1", INTN pin is enabled to output the interrupt signal of headphone jack detection. ALC Control (66H) LTM1-0: ALC1 limiter operation period at zero crossing disable (ZELMN bit = "1") (Table 17) Default: "00" (0.5/fs) The IPGA value is changed immediately when zero crossing is disabled (ZELMN bit = "1"). When the IPGA value is changed continuously, the change is done by the period specified by the LTM1-0 bits. WTM1-0: ALC1 Recovery Waiting Period (Table 19) Default: "00" (128/fs) WTM1-0 bits set a period of recovery operation when any limiter operation does not occur during the ALC1 operation. ZTM1-0: ALC1 zero crossing timeout selection (Table 18) Default: "00" (128/fs) When the IPGA performs zero crossing or timeout, the IPGA value is changed by the P WRITE operation, ALC1 recovery operation or ALC1 limiter operation (ZELMN bit = "0"). REV 0.6 - 79 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] ROTM: ALC2 Recovery Waiting Period (Table 39) 0: 2048/fs (Default) 1: 512/fs LMTH: ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level (Table 15) Default: "0" (-6dB/-8dB) The ALC1 limiter detection level and the ALC1 recovery counter reset level may be offset by about 2dB. RGAIN: ALC1 Recovery GAIN Step (Table 20) Default: "0" (0.5dB) During the ALC1 recovery operation, RGAIN bit sets the number of steps changed from the current IPGA value. For example, when the current IPGA value is "30H" and RGAIN bit is "1", the IPGA changes to "32H" by the ALC1 recovery operation and the output signal level is gained up by 1dB (=0.5dB x 2). When the IPGA value exceeds the maximum level (REF6-0 bits), the IPGA value does not increase. LMAT1-0: ALC1 Limiter ATT Step (Table 16) Default: "00" (0.5dB) During the ALC1 limiter operation, when IPGA value exceeds the ALC1 limiter detection level set by LMTH bit, LMAT1-0 bits set the number of steps attenuated from the current IPGA value. For example, when the current IPGA value is "47H" and LMAT1-0 bits is "11", the IPGA value decreases to "43H" when the ALC1 limiter operation starts, resulting in the input signal level being attenuated by 2dB (=0.5dB x 4). When the attenuation value exceeds IPGA = "00" (-8dB), it clips to "00". ZELMN: Zero crossing detection enable at ALC1 Limiter operation 0: Enable (Default) 1: Disable When the ZELMN bit = "0", the IPGA performs a zero crossing or timeout and the IPGA value is changed by the ALC1 operation. The zero crossing timeout is the same as the ALC1 recovery operation. When the ZELMN bit = "1", the IPGA value is changed immediately. ALC1: ALC1 enable 0: ALC1 Disable (Default) 1: ALC1 Enable ALC2: ALC2 enable 0: ALC2 Disable (Default) 1: ALC2 Enable Volume Control (68H) ATTS2-0: Volume control of signal from IPGA to Headphone/Speaker-Amp (Table 7) Default: "2H" (-12dB) ATTM: Volume control of signal from IPGA to Mono Line Output (Table 8) 0: 0dB (Default) 1: -4dB ATS: Digital attenuator transition time setting (Table 26) Default: "0" (531/fs) REV 0.6 - 80 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] Detect Result (6AH) DTMIC: MIC detection result (Read only, Table 13) 0: Microphone is not detected. 1: Microphone is detected DTHPJ: Headphone jack insertion detection result (Read only, Table 34) 0: Headphone jack is not inserted. 1: Headphone jack is inserted. DTPEN: Pen touch detection result when PM12AD bit = "0", PENINT bit = "1" and PINTR bit = "1" (Read only) 0: Pen is not touched. 1: Pen is touched. REV 0.6 - 81 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] 12bit ADC Control 1 (70H) A2-0, SER: 12bit ADC measurement item select (Table 44) Default: "0001" (TEMP0 temperature) ADMODE1-0: 12bit ADC measurement mode select (Table 48, Table 50) Default: "00" (74H Register Read) ADEXE1-0: ADEXE mode select (Table 52) Default: "00" (Mode 0) DLY3-0: Wait time select from mode setting to ADC execution (Table 46) Default: "0000" (1TS) MSR1-0: Measurement times select (Table 51) Default: "00" (4 times) ADFLT: 12bit ADC data filtering select (Table 47) 0: OFF (Default) 1: 4 data averaging PM12AD: 12bit ADC for touch screen controller power management (Table 6) 0: Power Down (Default) 1: Power Up REV 0.6 - 82 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] 12bit ADC Control 2 (72H) SLOT: 12bit ADC data reception method select (Table 43) 0: Register (Default) 1: Slot SLOTNO1-0: 12bit ADC measurement result output slot select (Table 49) Default: "00" (Slot 5) PINTE: 12bit ADC for touch screen controller power management (Table 45) 0: Power Down (Default) 1: Power Up PMVREF: Internal reference voltage for touch screen controller power management (Table 45) 0: Power Down (Default) 1: Power Up PINTR: DTPEN bit output enable for pen interrupt Default: "1" (ON) When PINTR bit is "1", pen interrupt is output at DTPEN bit. PENINT: INTN pin output enable for pen interrupt Default: "0" (OFF) When PENINT bit is "1", pen interrupt is output via INTN pin. GINT: Slot output enable for pen interrupt Default: "0" (OFF) When GINT bit is "1" and AC-link operates, pen interrupt is output at bit 0 of slot 12 on SDATAIN. SIWU: Warm reset by SDATAIN Enable 0: Disable 1: Enable (Default) 12bit ADC Data (74H, 76H, 78H) ADE: Measurement data valid flag (Read only) 0: Invalid 1: Valid A2-0: Measurement item (Read only, Table 44) D11-0: 12bit ADC measurement data (Read only) Vendor ID (7CH, 7EH) "A(41H), K(4BH), M(4DH), 16(10H)" (Read only) REV 0.6 - 83 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] SYSTEM DESIGN Figure 58 shows the system connection diagram for the AK4650. An evaluation board [AKD4650] is available which demonstrates the optimum layout, power supply arrangements and measurement results. Internal MIC MIC Jack 5V Battery 2.7 3.6V Regulator 0.1u 4.7u 0.1u 10u 2.2u 2.2k + 0.1u 0.1u 0.1u 2.2k NC 4.7n 4.7n 10k 10k VCOC1 IN2 AVDD VCOM AUXIN+ MPI EXT MPE NC 0.1u VCOC2 AVSS MVREF AUXIN- INT MDT AIN MICOUT 10u 0.1u XP TSVDD MOUT- MOUT+ 2.2k YP XN HPL HPR + 47u YN TSVSS AK4650VG HVSS HVDD + 0.1u 10u 2.2k Touch Screen + + 47u Headphone Jack IN1 0.1u VBAT SPP SPN + 4.7u VREF IOUT NC MUTET HDT 1u 8ohm Speaker LCD Driver ADEXE INTN XTO SDATA OUT DVSS1 DVSS2 SDATAIN SYNC MOUT2 MIN 0.1u 100k NC DVDD1 XTI BITCLK DVDD2 RESETN PLL1 TEST 10 + 10u 0.1u 0.1u 24.576MHz Controller Digital Ground Analog Ground Note 43. AVSS, DVSS, HVSS and TSVSS of the AK4650 should be distributed separately from the ground of external controllers. Note 44. Values of R and C in Figure 58 depend on each system. Note 45. All input pins except for internal pull-down pins should not be left floating. Figure 58. Typical Connection Diagram REV 0.6 - 84 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] 1. Grounding and Power Supply Decoupling The AK4650 requires careful attention to power supply and grounding arrangements. AVDD, DVDD, HVDD and TSVDD are usually supplied from the system's analog supply. If AVDD, DVDD and HVDD are supplied separately, the correct power up sequence should be observed. AVSS, DVSS, HVSS and TSVSS of the AK4650 should be connected to the analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4538 as possible, with the small value ceramic capacitor being the nearest. 2. Voltage Reference VCOM is a signal ground of this chip. A 2.2F electrolytic capacitor in parallel with a 0.1F ceramic capacitor attached to the VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from the VCOM pin. All signals, especially clocks, should be kept away from the VREF and VCOM pins in order to avoid unwanted coupling into the AK4650. 3. Analog Inputs The Mic, Beep and stereo line inputs are single-ended. AUX input is differential. The input signal range scales with nominally at 0.06 x AVDD Vpp for the Mic input, 0.6 x AVDD Vpp for the Beep input, stereo line input and AUX input, centered around the internal common voltage (0.45 x AVDD). Usually the input signal is AC coupled using a capacitor. The cut-off frequency is fc = (1/2RC). The AK4650 can accept input voltages from AVSS to AVDD. 4. Analog Outputs The input data format for the DAC is 2's complement. The output voltage is a positive full scale for 7FFFH(@16bit) and a negative full scale for 8000H(@16bit). Mono output from the MOUT2 pin and Mono Line Output from the MOUT+/MOUT- pins are centered at 0.45 x AVDD. Headphone-Amp and Speaker-Amp output are centered at HVDD/2. REV 0.6 - 85 - 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] PACKAGE 57pin BGA (Unit: mm) A 9 8 7 65 5.0 0.1 57 - 0.3 0.05 0.05 M S AB 4 32 1 A B C D E B 5.0 0.1 4.0 F G H J 0.5 0.5 S Material & Lead finish Package molding compound: Epoxy Interposer material: BT resin Solder ball material: SnAgCu REV 0.6 - 86 - 0.25 0.05 0.08 S 1.0MAX 2004/03 ASAHI KASEI AKM CONFIDENTIAL [AK4650] MARKING 4650 XXXX XXXX: Date code (4 digit) Pin #1 indication IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: a. A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. REV 0.6 - 87 - 2004/03 |
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